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We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: (i) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-H bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all &ldquo, samples&rdquo, in this ensemble we calculate time-0 currents (i.e. currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e. have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.

International audience

© 2019 IEEE. Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full (V g, V d) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages. ispartof: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) vol:2019-March ispartof: IEEE International Reliability Physics Symposium (IRPS) location:CA, Monterey date:31 Mar - 4 Apr 2019 status: published

© 1963-2012 IEEE. Operating temperature has a significant imp-act on the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ( Δ Neff) at operating condition typically shows an Arrhenius temperature dependence with EA 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77-373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture-emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total ΔV th measured in biaserature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. ispartof: IEEE TRANSACTIONS ON ELECTRON DEVICES vol:65 issue:9 pages:3689-3696 status: published

An on-wafer human metal model ESD measurement setup with voltage and current waveform measurement capability is presented. Using this setup, typical ESD protection structures and ESD protected circuits are characterized. A correlation between device responses on system-level ESD compared to component-level ESD stress like human body model is found to depend strongly on the device type.

Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.

Comparison of digital and analog Figures-of-Merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated.

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this work, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90 nm RF-CMOS process using wafer-level packaging (WLP) techniques. The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz WLP balun has been realized. The technology is demonstrated by a low-power 5GHz 90nm RF-CMOS VCO with a core current consumption of only 430 ?A from a 1.2 V supply, a phase noise of -112dBc/Hz at 1MHz offset and a tuning range of 530MHz.

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as 'plug-and-play',is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.

It has been known that using selective epitaxial growth (SEG) silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency ( max) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on dc C and RF performance of NMOS transistors. Up to a 28%–45% improvement in max is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain ( S/D) architecture. The maximum transconductance ( ) of the S/D device reaches a value of 1100 mS/mm, which in turn gives a very high of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.

© 2017 IEEE. A novel physically unclonable function (PUF) utilizing the intrinsic randomness of oxide breakdown (BD) positions in CMOS transistors is presented. The advantages of this approach are studied and validated by measurements on test-chips fabricated in a commercial 40nm CMOS process. Experiments show that the required soft BDs can be reliably generated in a sufficiently short period. The randomness of the utilized mechanism shows excellent properties, required for PUF applications: An overall bias of 0.498 and inter-chip hamming distance (HD) of 0.501. Further analysis of the current distributions reveals a dependence of operating voltage on readout resolution and window. Finally, dedicated experiments with external heating and embedded poly-heaters show that these soft BDs are stable and show no read-out errors up to operating temperatures of 600K.

© 2017 IEEE. A novel physically unclonable function (PUF) utilizing the intrinsic randomness of oxide breakdown (BD) positions in CMOS transistors is presented. The advantages of this approach are studied and validated by measurements on test-chips fabricated in a commercial 40nm CMOS process. Experiments show that the required soft BDs can be reliably generated in a sufficiently short period. The randomness of the utilized mechanism shows excellent properties, required for PUF applications: An overall bias of 0.498 and inter-chip hamming distance (HD) of 0.501. Further analysis of the current distributions reveals a dependence of operating voltage on readout resolution and window. Finally, dedicated experiments with external heating and embedded poly-heaters show that these soft BDs are stable and show no read-out errors up to operating temperatures of 600K.