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This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a $0.11~\mu \text{m}$ CMOS process using four metal layers with an active die area of 0.165mm2. It achieves a dynamic range (DR) of 96.3 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming $62.43~\mu \text{W}$ from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171dB.

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, $\beta $ -compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( $\beta $ ), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a $\beta $ of about 2.7 at 27 °C in a 0.18- $\mu \text{m}$ CMOS process. The proposed SC BGR achieves a $3\sigma $ inaccuracy of +0.02%, −0.12% from −40 °C to 125 °C. From a 1.8-V supply voltage, it consumes $17~\mu \text{A}$ at 27 °C and occupies an active area of 0.38 mm2.

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step.

An ultra-low-power 12-bit 200MS/s two-step pipelined SAR ADC is presented. In the first-stage SAR ADC, a separate DAC is applied with very small unit capacitors which generate the comparator decision threshold, thereby minimizing the required switching power. The dynamic register, which stores the comparator output, directly controls the DAC switch, dramatically reducing the SAR decision delay time. Based on the employed asynchronous SAR logic, the metastable state detection and correction logic can be implemented using a very simple digital logic. The prototype ADC in a 28nm CMOS process achieves a maximum SNDR of 64.8dB, resulting in a FoM of 7.7fJ/conversion-step.

This paper presents a 10-bit 900-MS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). A multiplying digital-to-analog converter (MDAC) using an open-loop amplifier is employed to increase the conversion speed efficiently. To reduce the complexity of the calibration logic for non-ideal open-loop gain stage, a reference scaling technique is adopted. A second stage 5-bit SAR ADC is implemented in current-mode with a gm-cell residue amplifier. The prototype ADC is fabricated in a 28 nm FDSOI CMOS process with an active die area of 0.014 mm2. Operating at 900-MS/s, the ADC achieves a signal-to-noise and distortion ratio of 48.9 dB and a spurious-free dynamic range of 61.2 dB, at Nyquist. It consumes 9.56 mW at a 1.0/1.2 V supply voltage, resulting in a Nyquist figure of merit of 46.7 fJ/conversion-step.

This paper presents a single-loop third-order delta-sigma modulator. It uses delayed feed-forward (FF) architecture to relax the op-amp requirement of the integrators. Noise-coupling technique is employed to obtain third-order noise shaping with two integrators. The prototype analog-to-digital converter (ADC) fabricated in a 0.18μm CMOS process achieves a 90.1 dB dynamic range (DR) and a 87.0 dB peak signal-to-noise and distortion ratio (SNDR) over a signal bandwidth of 160kHz with OSR of 32. The modulator occupies an active die area of 0.225 mm2, and its power consumption is 2.52mW from a 1.8V supply voltage.

This paper presents a single-trim switched-capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. A β-compensation technique, which is used in conjunction with mismatch averaging, and a discrete time (DT) domain curvature correction are proposed to minimize non-PTAT errors. The remaining PTAT errors are cancelled out by using a single room-temperature (27°C) trimming. Implemented in a 0.18μm CMOS, the proposed SC BGR achieves a 3σ inaccuracy of +0.02%, −0.12% and an average temperature coefficient (TC) of 4.3ppm/°C from −40°C to 125°C. It consumes 17μΑ at 27°C from 1.8V supply.

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the process-insensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm2 and consumes 2.63 mA with a 1.8 V supply voltage.

This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-shaping (SMASH) delta–sigma modulator. It uses source-follower-based integrators to efficiently increase the operating speed of a DT modulator. A SMASH topology that consists of two second-order low-distortion feed-forward stages provides an enhanced linearity by reducing the sensitivity to the non-ideal gain and distortion of the proposed integrator. The resolution of the proposed SMASH architecture is improved by eliminating the first-stage quantization noise from the output. In order to reduce power and area of the modulator, one 5-bit feedback digital-to-analog converter is shared for both stages, and the number of comparators for a 4-bit quantizer in the second stage is reduced by scaling the signal swing range. The prototype delta–sigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB signal-to-noise-and-distortion ratio (SNDR) in a 20-MHz bandwidth. From a 1.2-V supply voltage operating at a 500-MHz clock frequency, the total power consumption of the prototype modulator is 20.4 mW, corresponding to a Walden and Schreier figure of merits of 141.3 fJ/conversion-step and 165.7 dB, respectively.

In this study, we used a Ni/W/Ni-layered structure to provide low-resistive ohmic contacts with good thermal stability for both n-type and p-type 4H-SiC. As reference, we used Ni and Ni/Ti/Ni as control groups with specific contact resistivities, and we verified the thermal stability of the structures by specific contact resistivity measurements and thermal duration tests. We found that for both n-type and p-type semiconductors, Ni/W/Ni is superior in terms of thermal stability and specific contact resistivity. Using XRD, we also analyzed the components involved in ohmic contact and thermal stability tests.

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mW from a 1.0 V power supply. The prototype chip occupies 0.16 ㎟ using a 0.13 mm CMOS technology.

Continuous-rate all-digital reference-less clock and data recovery (CDR) circuit that utilises a sub-harmonic extraction scheme for wide-range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference-less all-digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 231 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.

This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes correlated-double-sampling (CDS) technique to attenuate flicker noise of the op-amp in the first integrator. The prototype analog-to-digital converter (ADC) is fabricated in a 0.18 µm CMOS process with an active die area of 0.119 mm2. It achieves a dynamic range (DR) of 101dB, a peak signal-to-noise ratio (SNR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 91.5 dB in a 24kHz signal bandwidth while consuming 1.55 mW from a 1.8 V power supply.

This paper presents a 10-bit 320-MS/s dual-residue pipelined SAR ADC. In the proposed ADC, an open-loop gain stage is employed without any calibration by relaxing the offset, gain, and linearity requirements of the inter-stage residue amplifier. Also, a binary search current interpolation is proposed for further quantization of the two residue signals. With a gm-cell residue amplifier and two 5-bit current interpolators, the second stage SAR operation is performed using a single comparator. The prototype ADC is fabricated in a 28 nm CMOS process with an active die area of 0.015$m m^{2}$. Operating at a sampling rate of 320 MHz, the ADC achieves a SNDR and a SFDR of 54.0 dB and 66.4 dB, respectively, at the Nyquist input frequency. It consumes 5.45 mW at a 1.0 V supply voltage, resulting in a Nyquist FoM of 41.6 fJ/conversion-step.

This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC–DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC–DC buck converter with an active die area of 0.28 mm2 was implemented using a 0.18 µm bipolar-CMOS–DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V.

This paper proposes a low-power rangescaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a samplingtime mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The firstand second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the firststage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a 0.18 μm CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of 1.43 mm 2 consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

Moving target has a non-coherent phase characteristic regardless of micro-Doppler effect caused by body motion, because the movement of the target changes the beat-frequency and its phase. A phase compensation method to remove the phase variations caused by movement is proposed. Using the proposed phase compensation method, it is possible to classify targets as pedestrians or automobiles based on the phase variance because pedestrians and automobiles have non-coherent and coherent phases, respectively. Through applying experimental data, the possibility of target classification is shown.

This paper presents a 4-channel analog front-end (AFE) for Electromyogram (EMG) acquisition systems. Each input channel consists of a chopper-stabilized instrumentation amplifier (IA) and a low-pass filer (LPF). A 15-bit analog-to-digital converter (ADC) with a buffer amplifier is shared with four input channels through multiplexer. An incremental ADC with a 1.5-bit second-order feed-forward topology is employed to achieve 15-bit resolution. The prototype AFE is fabricated in a 0.18 μm CMOS process with an active die area of 1.5 mm2. It achieves 3.2 μVrms input referred noise with a gain of 40 dB and a cutoff frequency of 500 Hz for LPF while consuming 3.713 mW from a 1.8V supply.

This paper presents a 2-2 discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator using source-follower-based open-loop integrators. The resolution of the SMASH delta-sigma modulator is enhanced by eliminating the first-stage quantization noise from the output. Using the proposed source-follower-based open-loop integrator, the operating speed of the modulator is efficiently improved. The prototype deltasigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB SNDR in a 20-MHz bandwidth. The modulator occupies an active area of 0.34 mm2, and its total power consumption is 20.4 mW from a 1.2-V supply voltage operating at a 500-MHz clock frequency.

This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 μm CMOS technology providing 0.35 μm thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSBrms/14 b consumes 192.9 mW at the 14 b 50 MS/s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies.

This work proposes a 12b 100 MS/s 0.11 m CMOS three-step hybrid pipeline ADC for high- speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual- channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 m CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm 2 and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented. The split time integration technique for implementing multi-bit digital-to-analog converter (DAC) without using DEM has been developed and used. In order to reduce power consumption and area, a successive approximation register (SAR) ADC is employed to function as both multi-bit quantizer and summing adder without using an additional amplifier. The proposed deltasigma modulator operates at a 640 kHz clock rate and dissipates 850 W with a 1.1 V supply. It achieves 81.8 dB dynamic range (DR), 76.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth. The core area is 235 m 2 in a 45-nm CMOS technology.

A second order delta-sigma analog-to-digital converter (ADC) including a bandgap reference, a bias circuit for sensor, and a digital filter for the interface of piezoresistive pressure sensor is presented. The proposed sensor interface circuit is designed to target a pressure range from 0 to 100 psi. The prototype sensor interface circuit is implemented in a 0.35 μm CMOS process. The single-loop, 1-bit, second-order delta-sigma ADC operates at OSR of 256 achieves 80.5 dB dynamic range (DR), 79.6 dB peak signal-to-noise ratio (SNR), and 74.4 dB peak signal-to-noise and distortion ratio (SNDR) over a signal bandwidth of 7.8 kHz with 3.3V supply while consuming 0.33mW including on-chip reference and bias current for sensor. (in Performance Summary: 0.95mW)

This paper presents a low distortion analog front-end (AFE) circuit to process electret microphone output signal. A source follower is employed for the input buffer to interface electret microphone directly to the IC with level shifting. A single-ended to differential converter with output common-mode control is presented to compensate the common-mode variation resulted from gate to source voltage variation in the source follower. A replica stage is adopted to control the output bias voltage of the single-ended to differential converter. The prototype AFE circuit fabricated in a 0.35μm CMOS technology achieves 68.2dB peak SNDR and 79.9dB SFDR over an audio signal bandwidth of 20kHz with 2.5V supply while consuming 1.05mW.

This brief presents a 10-bit 100-MS/s 1.2-V dual-channel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm2 using a 0.13-μm CMOS technology.

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software-defined radio systems requiring simultaneously high-resolution, low-power, and small chip area at high speed. The proposed calibration-free ADC employs a wide-band low-noise input sample-and-hold amplifier (SHA) along with a four-stage pipelined architecture optimizing scaling-down factors for the sampling capacitance and the input trans-conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal-insensitive 3-D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13µm 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64 and 61 dB and a maximum spurious-free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0mm2 consumes 140 mW at 150 MS/s and 1.2 V. Copyright © 2010 John Wiley & Sons, Ltd.

This work describes a 12-bit 100MS/s 0.13µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gate-bootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs based on slightly overlapped switching clocks. The interpolation, open-loop offset sampling, and two-step reference selection schemes for a back-end 6-bit flash ADC reduce both power consumption and chip area drastically compared to the conventional 6-bit flash ADCs. The prototype ADC in a 0.13µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively. The ADC shows a maximum SNDR and SFDR of 60.5dB and 71.2dB at 100MS/s, respectively. The ADC with an active die area of 0.92mm2 consumes 19mW at 100MS/s from a 1.0V supply. The measured FOM is 0.22pJ/conversion-step.

— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-digital converter (ADC) based on a fully differential class-AB switched operational amplifier achieves low power consumption with a differential input voltage of 2.4 Vp-p. A global-loop dynamic common-mode feedback circuit enables fully differential class-AB operation with dynamic current switching for power reduction. The prototype ADC shows a peak signal-to-noise-and-distortion ratio of 64.0 dB and a peak spurious-free dynamic range of 76.6 dB for a 31 MHz input signal at 50 MS/s while the measured differential and integral nonlinearities are within ±0.26 LSB and ±0.72 LSB, respectively. The prototype ADC in a 0.18 ?m 1P6M CMOS process consumes 18.4 mW at 50 MS/s and 1.8 V occupying an active die area of 0.26 mm2.

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 ㎷ without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a 0.18 ㎛ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 ㎑ fullscale input at 2 MS/s. The ADC with an active die area of 0.12 ㎟ consumes 3.6 ㎽ at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-?m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within ±0.30 LSB and ±0.95 LSB, respectively. The ADC occupies an active die area of 0.56 mm2 and consumes 51.6 mW at a 1.2 V power supply.

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

A 12-bit 40-kS/s VCM-based switching C-C successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The proposed SAR ADC exploits VCM-based switching method with a C-C segmented digital-to-analog converter (DAC) to reduce the size of the converter. Capacitive sub-DAC with buffer amplifier using offset cancellation is utilized to enhance the linearity of converter. Majority vote comparison technique is employed to alleviate comparator noise and to achieve high accuracy comparison. The prototype ADC is fabricated in a 0.18 μm CMOS process. The ADC shows maximum SNDR and SFDR of 57.1dB and 57.3dB with a 1.8V supply while consuming 66.7μW. It occupies an active die area of 0.22mm2.

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.

A 10-bit 20-MS/s dual-channel algorithmic analog-to-digital converter (ADC) using an improved clocking scheme is presented. The proposed ADC employs amplifier sharing technique with a conversion time scaling to reduce area and power. To achieve further improvement of conversion time scaling, dedicated MDAC sampling capacitors scaled with the accuracy requirement of each cycle are used. The ADC implemented in a 0.18µm CMOS process achieves 59.6dB SFDR and 54.3dB SNDR while consuming 8.96 mW per channel from a 1.8-V supply voltage.