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Background: Aptamers are currently being used in various fields including medical treatments due to their characteristics of selectively binding to specific molecules. Due to their special characteristics, the aptamers are expected to be used to remove radionuclides from a large amount of liquid radioactive waste generated during the decommissioning of nuclear power plants. The radiological effects on the aptamers should be evaluated to ensure their integrity for the application of a radionuclide removal technique.Materials and Methods: In this study, Monte Carlo N-Particle transport code version 6 (MCNP6) and Monte Carlo damage simulation (MCDS) codes were employed to evaluate the radiological effects on the aptamers. MCNP6 was used to evaluate the secondary electron spectrum and the absorbed dose in a medium. MCDS was used to calculate the DNA damage by using the secondary electron spectrum and the absorbed dose. Binding experiments were conducted to indirectly verify the results derived by MCNP6 and MCDS calculations.Results and Discussion: Damage yields of about 5.00×10-4 were calculated for 100 bp aptamer due to the radiation dose of 1 Gy. In experiments with radioactive materials, the results that the removal rate of the radioactive 60Co by the aptamer is the same with the non-radioactive 59Co prove the accuracy of the previous DNA damage calculation.Conclusion: The evaluation results suggest that only very small fraction of significant number of the aptamers will be damaged by the radioactive materials in the liquid radioactive waste. Keywords: Aptamer, Liquid Radioactive Waste, Decommissioning, Decontamination, Radiological Damage

In the hybrid main memory sub-system which consists of DRAM and phase change RAM (PRAM), DRAM is often used as a cache. Such a configuration of DRAM cache and PRAM main memory has two problems. First, it requires high bandwidth of data movement between DRAM and PRAM due to the large granularity (i.e., DRAM row) of caching. Second, the memory bandwidth of PRAM is not fully utilized since it can be accessed only by the DRAM cache thereby limiting the memory bandwidth of hybrid main memory to that of DRAM cache. In this paper, we propose a novel architecture where both DRAM and PRAM can be accessed in parallel for higher memory performance. We analyze that the performance and fairness of hybrid memory sub-system is limited by the stall time at the data queue of memory controller. In order to resolve this problem, we propose caching data selectively in a way to reduce stall time thereby reducing memory access latency and improving fairness. Our experimental results show significant improvements in performance (by an average of 21 percent), fairness (by 2.1 times), and energy consumption (by 10 percent) compared with the best of the existing methods in a multi-core system which consists of multiple CPUs and GPU.

The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 ∼ 2.99 times improvement in memory utilization in the latency-tolerant designs.

This paper describes the micromachined piezoelectric microspeakers that can produce the audible signal with 20 V peak-to-peak input voltages. The diaphragm size is 4 × 4 mm2 and the thickness of diaphragm is around 1 micron meter except partially etched piezoelectric area. The maximum sound output pressure of the microspeaker is even higher than ever before with a small diaphragm in high frequency range around 10 kHz. This successful result bases upon using high quality AlN thin film. The deposited AlN thin film shows c-axis oriented columnar structure and very fine grains. The highest SPL (Sound Pressure Level) measured from 300 Hz to 12 kHz shows about 100 dB around 10 kHz in case of circular type microspeaker and about 76 dB in case of cross type, respectively.

Juvenile hormone (JH) is a major insect gonadotropin. However, no endogenous types of JH have been found in beet armyworm, Spodoptera exigua. Here we analyzed the JH effect on vitellogenesis of S. exigua, which was used for determining the type of endogenous JHs in the species. Females were decapitated at different times after adult emergence to remove the source of JH. This treatment prevented vitellogenic development of S. exigua when the decapitation was executed as early as 4h after adult emergence. Both JH analogs, fenoxycarb and pyriproxyfen, induced vitellogenesis of the decapitated females. Similarly, JH I and JH II could induce vitellogenesis of the decapitated females, but not JH III. Follicle cell patency, allowing access of vitellogenin (Vg) in the hemolymph to the growing oocyte, was induced by the application of JH and JH analogs, but not by RH5992, an ecdysteroid agonist. Phenoxyphenyl compounds such as fenoxycarb, KS-175 (1-(4-phenoxyphenoxypropyl) imidazole), and T3 (L-3, 5, 3′-triiodothyronine) also significantly induced the follicle cell patency of S. exigua. Among JHs, JH I and JH II could significantly induce follicle cell patency, but not JH III. Both JHs and ecdysteroids could induce Vg biosynthesis. These results suggest that JH I and JH II can be the endogenous types of S. exigua and play roles in the vitellogenesis in both Vg biosynthesis of the fat body and Vg uptake by the growing oocytes.

As DRAM faces scaling limit, several new memory technologies are considered as candidates for replacing or complementing DRAM main memory. Compared to DRAM, the new memories have two major differences, non-volatility and write overhead in terms of endurance, latency and power. We built two different FPGA-based evaluation boards to evaluate hardware and software designs for new-memory based main memory; one with a DRAM subsystem having parameterizable latency and non-volatility emulation, and the other with the real chips of new memory namely phase-change RAM (PRAM). We experimented primitive functions and SQLite-based benchmarks on Linux, verifying the workings of new functionalities, e.g., nonvolatility and evaluating the impacts of new memory on software performance. In our experiments, we also demonstrated the impact of new memory-aware software/hardware designs on program performance on a DRAM/PRAM hybrid memory.

Effect of exogenous juvenile hormones (JHs) on pupal development was assayed in the beet armyworm, Spodoptera exigua. Fenoxycarb, a potent JH mimic, was applied topically to different ages of the pupae, and showed significant inhibition of normal adult eclosion even at 0.1 μg dose when it was applied at the early pupal stage (day 0). As the pupal development underwent, the susceptibility of the pupae fenoxycarb decreased. RH5992, a potent ecdysteroid mimic, did not, however, any similar inhibitory effect on the pupae. Natural JH types (JH I, JH II, and JH III) were applied on day 0 pupae to compare their inhibitory effects on adult eclosion. Both JH I and JH II significantly inhibited adult eclosion at 1.0 μg dose, but JH III did not even at 10.0 μg dose. It was noted that fenoxycarb-treated pupae showed little rectum development. Fenoxycarb did not, however, show any negative effect on the development of compound eye and wing imaginal discs, and on the pupal hemolymph protein pattern. These results suggest that there should be a commitment period requiring an absence of JH for a normal adult metamorphosis during early pupal development and that the endogenous type of JH in S. exigua is JH I or JH II or both JHs like other lepidopteran species.

Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).

3D stacked DRAM improves peak memory performance. However, its effective performance is often limited by the constraints of row-to-row activation delay (tRRD), four active bank window (tFAW), etc. In this paper, we present a quantitative analysis of the performance impact of such constraints. In order to resolve the problem, we propose balancing the budget of DRAM row activation across DRAM channels. In the proposed method, an inter-memory controller coordinator receives the current demand of row activation from memory controllers and re-distributes the budget to the memory controllers in order to improve DRAM performance. Experimental results show that sharing the budget of row activation between memory channels can give average 4.72% improvement in the utilization of 3D stacked DRAM.

Network-on-chip and memory controller become correlated with each other in case of high network congestion since the network port of memory controller can be blocked due to the (back-propagated) network congestion. We call such a problem network congestion-induced memory blocking. In order to resolve the problem, we present a novel idea of network congestion-aware memory controller. Based on the global information of network congestion, the memory controller performs (1) congestion-aware memory access scheduling and (2) congestion-aware network entry control of read data. The experimental results obtained from a 5x5 tile architecture show that the proposed memory controller presents up to 18.9% improvement in memory utilization.

Self-supervised learning of graph neural networks (GNNs) aims to learn an accurate representation of the graphs in an unsupervised manner, to obtain transferable representations of them for diverse downstream tasks. Predictive learning and contrastive learning are the two most prevalent approaches for graph self-supervised learning. However, they have their own drawbacks. While the predictive learning methods can learn the contextual relationships between neighboring nodes and edges, they cannot learn global graph-level similarities. Contrastive learning, while it can learn global graph-level similarities, its objective to maximize the similarity between two differently perturbed graphs may result in representations that cannot discriminate two similar graphs with different properties. To tackle such limitations, we propose a framework that aims to learn the exact discrepancy between the original and the perturbed graphs, coined as Discrepancy-based Self-supervised LeArning (D-SLA). Specifically, we create multiple perturbations of the given graph with varying degrees of similarity, and train the model to predict whether each graph is the original graph or the perturbed one. Moreover, we further aim to accurately capture the amount of discrepancy for each perturbed graph using the graph edit distance. We validate our D-SLA on various graph-related downstream tasks, including molecular property prediction, protein function prediction, and link prediction tasks, on which ours largely outperforms relevant baselines., NeurIPS 2022