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In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from −0.85 V to −0.74 V after applying a high gate bias stress at 150 °C for 10−2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device’s reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.

The compare operation is widely used in many applications, from fundamental sorting to primitive operations in the database and AI systems. We present SRAM-based 3-D-CAM circuit designs using a monolithic 3-D (M3D) integration process for realizing beyond-Boolean in-memory compare operation without any area overheads. We also fabricated a processing-in-memory (PiM) macro with the same 3-D-CAM circuit using M3D for performing massively parallel compare operations used in the database, machine learning, and scientific applications. We show various system designs with the 3-D-CAM supporting operations, such as data filtering, sorting, and sparse matrix–matrix multiplication (SpGEMM). Our systems exhibit up to $272\times $ , $200\times $ , and $226\times $ speedups and $151\times $ , $37\times $ , and $156\times $ energy savings compared to systems using near memory compute for the data filtering, sorting, and SpGEMM applications, respectively.

With careful planning and a focus on developing expertise, government policy has helped Taiwan become a centre for semiconductor innovation.

Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with stacked tunneling layer were studied in this work. The programming speeds of poly-Ge tri-gate JL flash device with GeOx/Al2O3/SiO2 tunneling layer are faster than those with GeOx/Al2O3 or GeOx/SiO2 ones, thanks to the modified electric field in the tunneling layer. Better retention characteristics are also achieved due to a larger barrier height and physical thickness, because Ge diffusion is effectively suppressed by adding an Al2O3 between GeOx and SiO2, which can improve the quality of tunneling layer. A poly-Ge CT flash device fabricated with low-temperature process is promising for embedded memory in Ge CMOS or 3D IC.

The operation characteristics of polycrystalline Si (poly-Si) gate-all-around (GAA) junctionless (JL) charge-trapping (CT) flash memory devices with the Zr-based stacked trapping layer were studied in this work. Devices with the Si3N4/ZrO2 stacked trapping layer show enhanced erasing speeds and comparable retention characteristics in comparison to Si3N4/HfO2 due to many shallow energy traps and smaller valance band offset in the ZrO2 layer. By inserting Al2O3 between Si3N4 and ZrO2 trapping layer, the retention and endurance characteristics are improved. The erasing speed can be further improved by a Zr-rich oxide layer near the tunneling oxide since the energy barrier can confine more injected electrons near the tunneling oxide. The retention characteristic can be improved without sacrificing the erasing speed because some of the shallow traps can be passivated by NH3 plasma treatment on ZrO2. Hence, the ZrO-based stacked trapping layer is very promising for the poly-Si GAA JL CT flash devices for nonvolatile memory applications.

In this study, the device characteristics of dual-gate GaN high-electron-mobility transistors (HEMTs) were determined. The research investigated an enhancement-mode (E-mode) GaN HEMT with a second gate connected to the source and located between the main gate and drain. Two dual-gate GaN HEMTs with different second-gate designs, using Schottky or metal–insulator–semiconductor (MIS) contacts, were simulated and fabricated, and the direct current of the devices was investigated. In device simulation, p-GaN gates were used to achieve E-mode operation in HEMTs. Technology computer-aided design (TCAD) simulation indicated that the saturation drain current (ID, sat) of devices with Schottky and MIS second gates was 88% and 38% lower than that of a single gate structure, while increasing on resistance (Ron) by 31% and 8%, respectively. In device fabrication, a Schottky and MIS second gate were respectively added to an E-mode p-GaN gate HEMT and an E-mode recesses-gate GaN MIS-HEMT. Compared with single-gate structures, the devices with a Schottky and MIS second gates reduced ID, sat by 75% and 32%, respectively, while increasing Ron by 25% and 6%, respectively. The measured electrical characteristics indicate the same trend obtained from TCAD simulation: The dual-gate design can improve the short-circuit capability of GaN HEMTs by reducing the ID, sat under on-state and high-current conditions.

Four specimen patterns with the microstructure of a microcopper wire are deposited on the Si-wafer substrate plus thermal oxide (SiO2) film as the top layer. Each pattern was prepared to have two kinds of specimens, including with and without ultrathin carbon film between the copper wire and the top layer (SiO2). The effect of carbon film on electrical properties is evaluated via the measurements of the I (current)–V (voltage) curve, sheet electrical resistance, current leakage, and its ratio and effective permittivity. A rapid thermal annealing (RTA) technique is provided as an economic and efficient method to grow the ultrathin carbon film rapidly as the interlayer. Appropriate choices of 900 °C and 3 min as the annealing temperature and time can produce ultrathin carbon film with nearly 100% coverage of the copper surface. The sheet resistance of specimen demonstrates the behavior exactly opposite to that of the carbon film coverage of wire surface. The combined effect of elevating the voltage and annealing temperature of the specimen with carbon film on the current leakage is much lower than that arising in the specimen without carbon film, so long as the carbon films operating at that temperature (between 350 and 500 °C) are still sustainable. The differences in current leakage and effective permittivity between these two kinds of specimen are significantly increased by raising the temperature. The intensity (IC) of copper diffusions into the SiO2 layer in the specimens with the carbon film demonstrates behavior similar to that of current leakage (CL). The IC and CL values for the temperatures ≦ 350 °C are much lower than those obtained at 500 °C.

In the present study, upper and lower substrates made of p-type Si were bonded using benzocyclobutene (BCB) glue, which was then solidified via rapid thermal annealing at various chamber atmospheres. Inductively coupled plasma was applied to prepare through-silicon via (TSV) holes that penetrated the wafer-BCB-wafer (WBW) composite specimen. SiO2 and Ti films and copper pillars were deposited and filled in sequence to form the WBW TSV structure. These specimens were prepared for thermal tests to determine the earliest failure (fracture) time (Tfailure) for the Ti and SiO2 films and the time required for electrical current breakdown (TBD) in the specimens. Theoretical models, including the Johnson-Cook (J-C) fracture model and a numerical scheme, were developed to predict the Tfailure values for the Ti and SiO2 films. Black’s equation was applied to determine the variations of specimen activation energy with externally applied bottom surface temperature and electrical voltage. The numerical results for (Tfailure)Ti, (Tfailure)SiO2, and TBD are obtained quite close to those from the experiments. The elastic modulus of the solidified BCB material can be increased by fabricating the WBW structure under high vacuums. A relatively lower BCB elastic modulus can lower the maximum strain energy density required for fracture in the SiO2 film of the TSV structure, thus effectively increasing TBD. The rate of effective activation energy is the dominant factor for TBD. The effective activation energy in the preparation of BCB bonding decreases with increasing the vacuum.

The advanced supercritical fluid (SCF) technique was applied to reduce defects in the amorphous silicon thin-film layer and enhance the efficiency of a heterojunction (HJT) solar cell from 18.1% to 19.6%. An amorphous silicon thin-film layer has been used as a passivation layer between the substrate and electrode contact in HJT solar cells; however, many dangling bonds exist in the amorphous silicon thin-film layer. Therefore, the SCF technique was developed to passivate defects. The advantage of a supercritical state is high penetrability and low temperature. Thus, this SCF treatment can passivate defects in the completed device without changing the original fabrication process. After treatment, the passivation of dangling bonds was examined using Fourier-transform infrared spectroscopy, which confirmed the improved Si–H bonding. Moreover, electrical properties such as open-circuit voltage, short-circuit density, efficiency, shunt resistance, and leakage current were measured to confirm the enhancement. A simulated light source of 1 kW M−2 global AM1.5 spectrum was used to analyze the increase in cell efficiency, and the dark current was analyzed to confirm the leakage current improvement. Finally, a model for explaining the phenomenon in cells after treatment was developed.

A laser-buffer layer of SiO2/W/SiO2 with a high reflectivity at 10.6 μm enables CO2 laser treatment for the source/drain dopant activation of poly-Si nanoscale field-effect transistor (nano-FET) (Wch/Lg = 70/70 nm) on the flexible polyimide substrate. The laser-buffer layer thermally modified by CO2 laser reduces the sheet resistance of the source/drain to 1.4 kΩ/sq. at low laser energy of 15 W and low substrate temperature of 125 °C. The flexible nano-FET (nano-fFET) exhibits a subthreshold swing (S.S) of 84 mV/dec. and a low drain-induced barrier lowering of 202 mV/V at a bending radius of 10 mm. Low degradation rate of S.S and threshold voltage (Vth) for single- and multi-channel nano-fFETs arises from oxide-trap predomination after long time hot-carrier stress as demonstrated by a ΔVth power-factor of ∼0.2.

The SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2 and Si3N4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.

A single-crystal-island (SCI) technique is demonstrated using low thermal budget pulse laser process to fabricate single-crystal islands for monolithic 3D back-end-of-line (BEOL) FinFET circuits. The single-crystallinity are verified with SECCO etch, HREM, TEM, and EBSD. BEOL FinFETs fabricated in the designed single-crystal Si islands exhibit excellent electrical performance and low intra-island variability. To mitigate the effects of island-to-island device variation due to random island crystal orientations, crystal-orientation-tolerant voltage regulator is further proposed by allocating power gating (PG) cells among multiple Si islands, and 42% power noise suppression can be achieved.

This paper demonstrates the first Monolithic 3D+-IC based Compute-in-Memory (CiM) Macro performing massively parallel beyond-Boolean operations targeting database and machine learning (ML) applications. The proposed CiM technique supports data filtering, sorting, and sparse matrix-matrix multiplication (SpGEMM) operations. Our system exhibits up to 272x speedup and 151x energy savings compared to the ASIC baseline.

For the first time, ultrafast laser annealed BEOL gate-all-around (GAA) transistor and FeFET memory were demonstrated with monolithic 3D near-memory-computing (NMC) circuit. The GAA MOSFETs employing ultrafast picosecond visible laser dopant activation exhibit record-high Ion (nFETs=407 uA/um, pFETs=345 uA/um). The BEOL FeFETs memory exhibits large memory window ΔV th = 1.2V, more than 106 cycle endurance. Moreover, the 3D stackability of the GAA MOSFETs and FeFET memory bit cell enable reduces the area of the NMC circuitry and improve the readout throughput.

In this work we propose a first attempt in the fabrication of a family of monolithic GaN-based quaternary multi-value logic gates (MVL), including QNOT, QNOR, and QNAND in a process flow compatible with enhancement mode (E-mode) power HEMT (BV > 650 V). Integration of MVL with GaN power HEMTs increases logic-state density and allows for the design of smart gate drive circuits with reduced switching loss and ringing when compared to circuits using discrete devices. Using TCAD and SPICE device models calibrated against experimental data we demonstrate the functionality of a quaternary inverter with noise margins NML and NMH above 60% and 50% of the logic state voltage range, respectively. Quaternary logic gates show an average reduction of 27% in area utilization when compared to binary logic gates. Additionally, the layout of a quaternary 16-bit DEMUX circuit is projected to occupy 22.5% less area than its binary equivalent. The application of quaternary MVL to digital control circuits for GaN power HEMTs is expected to reduce total circuit area and consume less power than a binary counterpart.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 &deg, C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 &micro, A/&micro, m (n-type) and 297 &micro, m (p-type) @ Vth &plusmn, 0.8 V, and higher Ion/Ioff (&gt, 105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(&Omega, )-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (10 2 ~10 5 ) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.

For the first time, below 400°C-fabricated poly-Si MOSFETs and 6T -SRAM fabrication process was demonstrated on polyimide (PI) substrate for flexible and transparent monolithic 3DIC. Key enablers are 400–900 nm transparent laser-stop layer (LsL), laser-crystallized/CMP-thinned poly Si channel and pulse UV-laser S/D activation. These advanced low thermal budget fabrication technologies enable stackable polySi MOSFETs on flexible 6” -wafer-scale PI substrate with high device uniformity $(\mathrm{V}_{\mathrm{th}}$ ‘SS~16.2%/16.6%) and bending stability $(\mathrm{V}_{\mathrm{th}}/\mathrm{SS}\sim 4.2\%/9.8\%)$ after cycle-bending at radius of 10mm. Such CMOS compatible technologies envision flexible 3D heterogeneous integration of circuits/optical sensors for human-skin adaptable Internet of Things (IoT) chips.

For the first time, below 400°C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I on /I off ratio (~108) with low I off (pFETs

Selenium (Se) is one of the potential candidates as photodetector because of its outstanding properties such as high photoconductivity (∼8 × 104 S cm–1), piezoelectricity, thermoelectricity, and nonlinear optical responses. Solution phase synthesis becomes an efficient way to produce Se, but a contamination issue that could deteriorate the electric characteristic of Se should be taken into account. In this work, a facile, controllable approach of synthesizing Se nanowires (NWs)/films via a plasma-assisted growth process was demonstrated at the low substrate temperature of 100 °C. The detailed formation mechanisms of nanowires arrays to thin films at different plasma powers were investigated. Moreover, indium (In) layer was used to enhance the adhesive strength with 50% improvement on a SiO2/Si substrate by mechanical interlocking and surface alloying between Se and In layers, indicating great tolerance for mechanical stress for future wearable devices applications. Furthermore, the direct growth of Se NWs...

Recent monolithic 3-D integrated-circuit (3D-IC) technology tends to induce stronger driving capability in pMOS transistors, compared to that obtained using existing processes. Thus, conventional 6T SRAMs suffer degradation in access speed and write margin when used in monolithic 3D-ICs. This letter proposes a dual-split-controlled 4P2N (DSC-4P2N) SRAM with corresponding read and write assist schemes capable of providing a larger cell read current and higher write margins compared to 4N2P SRAMs implemented in monolithic 3D-ICs. The proposed DSC scheme improves $4.8\times $ in read stability compared to 4P2N SRAM without DSC. A fabricated DSC-4P2N SRAM in monolithic 3D-IC was shown to outperform the previous 6T SRAMs.

In the present study, the experimental results of the thermally induced failure (fracture) time for the components of copper through‑silicon via (TSV) structures and the time for electrical current breakdown (TBD) are obtained to investigate the effects of the thickness of the SiO2 film and the operating temperature. The numerical scheme is also developed to solve the distributions of transient temperature and stress in the specimen and the equivalent stress/strain for the elements in the Ti, SiO2 and Si components of the TSV structure. The equivalent element stress solutions incorporating with the Johnson-Cook (J-C) fracture model are provided to identify the earliest failure element and time in each of these three components and the TBD of the structure via the definition for the D factor. The applied models and numerical scheme are confirmed to be trustworthy from the comparison of the numerically predicted and experimental results for these failure time parameters. The effects of the operating temperature of specimen's bottom surface and the film thickness of SiO2 on these time parameters have been evaluated precisely. The TBD time is elongated by increasing the thickness of either SiO2 or Ti film if the bottom surface is operating at a fixed temperature. The earliest failure time (tfailure) for the components of Ti, SiO2 and Si wafer and the TBD are always reduced by the rise of operating temperature.

A Ge0.955Sn0.045 nMOSFET with a record high mobility of 440 cm2/V $\cdot $ s is demonstrated in this letter by a gate-first process. By low-temperature chemical vapor deposition, high-quality GeSn films were epitaxially grown. The ambipolar leakage is effectively suppressed by the low-thermal-budget microwave annealing (MWA) step. Furthermore, the peak mobility in the device after the MWA step is enhanced by a factor of two compared with those after rapid thermal annealing. This can be attributed to the weaker Coulomb scattering at the oxide interface after the MWA step, suggesting that MWA is effective for dopant activation and a better oxide interface quality at the same time.

This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains with a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from un-melted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect hole mobility of 447 cm2V−1s−1 with minor performance deviation.

We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 °C. The AlN was grown by N2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H2/NH3 plasma pre-treatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V th), corresponding to a 40.2% of current collapse at 150 °C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.

An inductively coupled plasma (ICP) process was used to synthesize transition metal dichalcogenides (TMDs) through a plasma-assisted selenization process of metal oxide (MOx) at a temperature as low as 250 °C. In comparison with other CVD processes, the use of ICP facilitates the decomposition of the precursors at low temperatures. Therefore, the temperature required for the formation of TMDs can be drastically reduced. WSe2 was chosen as a model material system due to its technological importance as a p-type inorganic semiconductor with an excellent hole mobility. Large-area synthesis of WSe2 on polyimide (30 × 40 cm2) flexible substrates and 8 in. silicon wafers with good uniformity was demonstrated at the formation temperature of 250 °C confirmed by Raman and X-ray photoelectron (XPS) spectroscopy. Furthermore, by controlling different H2/N2 ratios, hybrid WOx/WSe2 films can be formed at the formation temperature of 250 °C confirmed by TEM and XPS. Remarkably, hybrid films composed of partially reduced...

It is widely known that thinner Si substrate is the main path for lower $/Watt HIT solar cells due to improved charge collection, reduced bulk and total recombination, and fewer raw material consumption (Panasonic, IEEE Journal of Photovoltaics., vol. 4, p. 96, 2014). Nonetheless, thin substrates always lead to low mechanical stability and wafer breaking. In this work, spray coated 50 nm graphene layer is used as the back electrode in Si HIT solar cells to enhance the mechanical stability. With the incorporation of graphene as the back electrode in Si HIT solar cells, remarkable improvements in substrate mechanical strength are achieved. Without the degradation of HIT solar cell efficiency, hardness is increased nearly twofold from 902 to 1747 HV. The Young's modulus is increased from 93.9 to 140.1 GPa while the ultimate tensile strength is increased from 96.71 to 273.68 MPa. Low-cost chemical exfoliation method and low-temperature (150 °C) spray coating method have been employed for the preparation and deposition of thin graphene back electrode, respectively. In addition, unlike the graphene as the substitute for ITO in OLED applications, the graphene strengthened thin silicon substrate technology here imposes no additional constraint on the graphene electrode transparency since it is used as a back electrode. We, thereby, believe that our proposed method is effective for attaining higher efficiency and lower $/Watt thin Si HIT solar cell technology with enhanced mechanical strength.

In this research, Finite Element Method (FEM) is used to simulate transient thermal conduction in the monolithic three-dimensional integrated circuit (3DIC) with a novel location-controlled-grain (LCG) technique. Through this method, the impact of laser flux, amorphous Si thickness and interlayer dielectric (ILD) thickness on that model can be investigated. Furthermore, with the assistance of thermal damage simulation, we can utilize the optimal process parameters in this state-of-the-art technique to accelerate the development of advanced semiconductor technologies.

For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D+-IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>106) that enable ultra-low power operation $(\mathrm{V}_{\text{DD}}=100\text{mV})$ of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing ( $385\ \mu \mathrm{A}/\mu \mathrm{m}$ ), and high I on /I off (>106). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal, the defect-free Ge channel can be formed on nothing. The ${p}$ -channel triangular Ge GAA FET with fin width ( ${W} _{\mathrm{ fin}}$ ) of 52 nm and Lg of 183 nm has $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}} = 10^{5}$ , SS = 130 mV/dec, and Ion = 235 $\mu \text{A}/\mu \text{m}$ at -1 V. Next, due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the $n$ -channel triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced Ion with respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can be further improved if superior gate stack than EOT = 5.5 nm and Dit $= 1\times 10^{12}$ cm $^{-2} \cdot $ eV $^{-1}$ is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defect-free suspended channel, nFET and pFET with excellent performance have been demonstrated, including an $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ratio exceeding $10^{8}$ , the highest ever reported for Ge-based pFETs. The TMD FinFET devices are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS2 covered on Si fin and nanowire resulted in improved (+25%) $\text{I}_{on}$ of the FinFET and nanowire FET. The PFETs also operated effectively and the N/P device $\text{V}_{\mathrm{ th}}$ are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide enables 0.5 V of $\text{V}_{\mathrm{ th}}$ shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

A progressing non-toxic plasma-enhanced solid Se vapor selenization process (PESVS) technique, compared with hydrogen-assisted Se vapor selenization (HASVS) to achieve a large-area (30×40 cm2) Cu(In,Ga)Se2 (CIGS) solar panel with enhanced efficiencies from 10.8% to 13.2% (14.7% for active area), was demonstrated. The bonding of Se was partially broken by ICP plasma treatment and these Se radicals are helpful to enhance reaction activity for following selenization process at an extremely low temperature of 330 °C. The effects of plasma steps, plasma power, selenization temperature and optimized conditions were thoroughly studied in detail. The remarkable enhancement of the efficiency is ascribed to the better crystallinity, enlarged grain size, less Se vacancy and uniform depth distribution of Ga. From reaction kinetics point of view, PESVS provides extra energy to crack Se, resulting in the decrease in reaction activation energy. The PESVS methodology was also applied to low temperature (450 °C) selenized CIGS thin film solar panel with uniform conversion efficiency more than ~10%. Furthermore, a large-area flexible stainless steel substrate with remarkable conversion efficiency of ~6.8% without Na addition was demonstrated. We believed that this work can provide a facile approach of low temperature selenization on flexible substrate applications or fast selenization for throughput consideration, thus stimulating the mass-production in large scale CIGS PV industry.

Three-dimensional sequentially stackable high- $k$ /metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and postsurface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 $\mu \text{A}/\mu \text{m}$ ), and $I_{{\mathrm{\scriptscriptstyle {on}}}}/I_{\mathrm{\scriptscriptstyle {OFF}}}$ ratio ( $> 10^{5})$ . Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low $V_{\mathrm {dd}}$ (0.6 V) operable inverter.

We report on the fabrication of a robust and flexible transparent electrode to replace costly and fragile indium tin oxide (ITO) used in flexible Cu(In,Ga)Se2 solar cells, composed of an aluminum doped zinc oxide (AZO)/Ag-nanowires/aluminum doped zinc oxide (AZO) (AAA herein) sandwich structure. The Ag-NWs networks form low-resistance, long-range pathways throughout the electrode that are able to maintain efficient charge carrier collection and extraction after strenuous mechanical bending. The improved durability of the AAA electrode enables our CIGS solar cells to maintain ∼95% of their initial power conversion efficiency, following 1000 bending cycles. In comparison, devices fabricated using AZO and ITO electrodes are only able to maintain ∼57 and ∼5%, respectively, due to crack formation and delamination of the films. This AAA sandwich structure electrode could therefore serve as a high-performance electrode for numerous flexible optoelectronic applications.

Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal, the defect-free Ge channel can be formed on nothing. The p-channel triangular Ge GAA FET with fin width (Wfin) of 52 nm and Lg of 183 nm has Ion/Ioff = 105, SS = 130 mV/dec, and Ion = 235 μA/μm at -1 V. Next, due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the n-channel triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced Ion with respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can be further improved if superior gate stack than EOT = 5.5 nm and Dit = 1×1012 cm-2·eV-1 is used. The Ion can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defect-free suspended channel, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs. The TMD FinFET devices are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS2 covered on Si fin and nanowire resulted in improved (+25%) Ion of the FinFET and nanowire FET. The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

Designing an efficient emitter design is an important step for achieving a highly efficient TPV conversion process. Wavelength-selective emissivity, spectra match between the emitter and TPV cells, and high thermal stability are three main characteristics that must be considered before implementing the emitter. In this work, an indium tin oxide (ITO)/sapphire emitter structure is investigated for TPV application over the temperature range from 200°C to 1000°C. A 1-µm-thick ITO layer is deposited on a 650-µm-thick sapphire substrate. In addition, 50-nm-thick SiO2 is deposited on top of the ITO to enhance the performance of emitter at high temperatures. High-temperature emissivity and absorptivity measurement of the emitter samples are obtained using FTIR and a Hitachi U-4100 spectrophotometer, respectively. The resultant SiO2/ITO/sapphire/stainless-steel planar emitter structure has selective emission with high emissivity of ∼0.8 in the 1–1.6 µm wavelength regime at 1000°C. This emission range lies at the bandgap edge of silicon TPV cells and thus can be used to harness the true potential for making a low-cost thermophotovoltaic system.

We report heterogeneously integrated sub-40nm epi-like monolithic 3DIC with vertical ReRAM and memory computing (NMC) circuit. High driving current multi-channel UTB-MOSFETs (3.3/1.4 mA$/\mu \mathrm {m}$ for N/P FETs) was realized by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO 2 far-infrared laser annealing (CO 2 -FIR-LA) activation technologies that enable driving 20nm 4-layer vertical ReRAM (Set/Reset $ \lt 1.2\mathrm {V}/1.8\mathrm {V}$, 3-bits/cell). Furthermore, the ultra-low threshold voltage of NC-FinFETs and the differential output of SRAM readout enable 50 +% area reduction in the near-memory computing circuitry. The unique TSV-free monolithic $3\mathrm {D} ^{+}$ IC process provides the superiority in 3D hetero-integration to realize low cost, small footprint, fully functionalized 3D IoTs chip.

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed two-layer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

Direct reduction of metal oxides into a few transition metal dichalcogenide (TMDCs) monolayers has been recently explored as an alternative method for large area and uniform deposition. However, not many studies have addressed the characteristics and requirement of the metal oxides into TMDCs by the selenization/sulfurization processes, yielding a wide range of outstanding properties to poor electrical characteristics with nonuniform films. The large difference implies that the process is yet not fully understood. In particular, the selenization/sulfurization at low temperature leads to poor crystallinity films with poor electrical performance, hindering its practical development. A common approach to improve the quality of the selenized/sulfurized films is by further increasing the process temperature, thus requiring additional transfer in order to explore the electrical properties. Here, we show that by finely tuning the quality of the predeposited oxide the selenization/sulfurization temperature can be largely decreased, avoiding major substrate damage and allowing direct device fabrication. The direct relationship between the role of selecting different metal oxides prepared by e-beam evaporation and reactive sputtering and their oxygen deficiency/vacancy leading to quality influence of TMDCs was investigated in detail. Because of its outstanding physical properties, the formation of tungsten diselenide (WSe2) from the reduction of tungsten oxide (WO x) was chosen as a model for proof of concept. By optimizing the process parameters and the selection of metal oxides, layered WSe2 films with controlled atomic thickness can be demonstrated. Interestingly, the domain size and electrical properties of the layered WSe2 films are highly affected by the quality of the metal oxides, for which the layered WSe2 film with small domains exhibits a metallic behavior and the layered WSe2 films with larger domains provides clear semiconducting behavior. Finally, an 8'' wafer scale-layered WSe2 film was demonstrated, giving a step forward in the development of 2D TMDC electronics in the industry.

Luminescent down-shifting (LDS) phenomenon has been employed to enhance the HIT solar cell efficiency. The efficiency and J SC are increased by 2.3% and 11.5% respectively. External quantum efficiency (EQE) data supports our claim.

This paper presents the first monolithic 3D vertical cross-tier computing-in-memory (CIM) SRAM cell fabricated using low cost TSV-free FinFET-based 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle. We fabricated stackable multi-fin single-grained Si FinFET using low thermal-budget CO 2 far-infrared laser annealing (FIR-LA) for activation and self-aligned silicide. The proposed device achieved high Ion (320 μA/μm (n-FET) and 275 μA/μm (p-FET)) and high I on /I off (>107). The proposed scheme enables the fabrication of energy and area efficient circuits for cost-aware intelligent IoT devices. For proposed 9T CIM SRAM cell, the monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.

Display Omitted In-situ doped poly-Si on vertically stacked JL flash memory devices are studied.Devices with in-situ doped (ISD) poly-Si channel show a large disturb-free window.Fast programming/erasing speeds, good retention and endurance are obtained.ISD poly-Si is promising for future three-dimensional CT flash device. Effects of in-situ doped (ISD) polycrystalline silicon (poly-Si), which serves as the source, drain and channel, on vertically stacked junctionless (JL) charge-trapping (CT) flash memory devices are investigated for the first time. The vertically stacked JL devices formed by ISD poly-Si channel show minimized program disturb with a large disturb-free window of 4.5V even when a low program-inhibit voltage (Vinhibit) of 6V is applied. It can be attributed to the fast programming speed of ISD JL device. Fast programming/erasing (P/E) speeds, good retention and endurance characteristics are also obtained. Therefore, ISD poly-Si is promising for future three-dimensional (3D) CT flash integration.