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58 results on '"Chadi Jabbour"'

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1. A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems

2. A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation

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3. Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications

4. Examining satellite images market stability using the Records theory: Evidence from French spatial data infrastructures

5. Impact assessment of a satellite data infrastructure: application to the management of clear cuts in France

6. Reconfigurable Adaptive Channel Sensing

7. Évaluation socio-économique des Infrastructures de Données Spatiales. Retours d’expérience et recommandations méthodologiques

8. Wide frequency characterization of Intra-Body Communication for Leadless Pacemakers

9. Physically-Derived 3-Box Power Amplifier Model

10. Digital post-distortion of radio receivers and analog-to-digital converters

11. Time or frequency interleaved analog-to-digital converters

12. System Design for Direct RF-to-Digital <tex-math notation='LaTeX'>$\Delta\Sigma$</tex-math> Receiver

13. Memory aware physically enhanced polynomial model for PAs

14. Wide band digital predistortion using iterative feedback decomposition

15. A low-power high-performance digital predistorter for wideband power amplifiers

16. FFT-Based Limited Subband Digital Predistortion Technique for Ultra Wideband 5G Systems

17. All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

18. Human Body Communication Channel Characterization for Leadless Cardiac Pacemakers

19. Wideband power amplifier predistortion: Trends, challenges and solutions

20. Fully-Digital Blind Compensation of Non-Linear Distortions in Wideband Receivers

21. An FIR Memory Polynomial Predistorter for Wideband RF Power Amplifiers

22. Fully Digital Feedforward Background Calibration Of Clock Skews For Sub-sampling TIADCs Using The Polyphase Decomposition

23. Delay-Reduction Technique for DWA Algorithms

24. A reconfigurable low-pass/high-pass $$\varDelta \varSigma$$ Δ Σ ADC suited for a zero-IF/low-IF receiver

25. A continuous-time direct RF-to-digital ΔΣ receiver

26. A CMOS 65nm 120 dB Stacked A/D Converters receiver for long wavelength radio astronomy observations

27. Estimation techniques for timing mismatch in Time-interleaved Analog-to-Digital Converters: Limitations and solutions

28. Cognitive computation and communication: A complement solution to cloud for IoT

29. A multi-channel ΣΔ modulator for subband digital predistortion with LTE signals

30. A flexible receiver using ΔΣ modulation

31. A comparison between high-pass and low-pass $$\Updelta\Upsigma$$ modulators

32. A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters

33. Novel architecture for high-pass cascaded ΔΣ modulator

34. Tutorial 1: Lab-on-a-chip based on CMOS technology: Parts, applications, challenges and future trends

35. Adaptive digital pre-distortion for future wireless transmitters

36. Hardware Implementation of All Digital Calibration for Undersampling TIADCs

37. Performance study of nonlinearities blind correction in wideband receivers

38. A flexible direct delta-sigma receiver for GSM/WCDMA/LTE

39. A Fully Digital Background Calibration of Timing Skew in Undersampling TI-ADC

40. A novel dynamic element matching technique suited for high pass ΔΣ ADCs

41. Direct delta-sigma receiver: Analysis, modelization and simulation

42. A Low Power RC Time Constant Auto-tuning circuit for RC-integrators in High Linearity Continuous-Time Delta Sigma modulators

43. High pass filter implementation comparison in unity STF high pass ΔΣ modulator

44. High-pass or low-pass ΣΔ modulators?

45. A novel design methodology for multiplierless filters applied on ΔΣ decimators

46. A low-power ΣΔ ADC optimized for GSM/EDGE standard in 65-nm CMOS

47. A LP/HP UMTS/GSM ΣΔ ADC suited for a Zero-IF/Low-IF receiver

48. A new interpolation technique for TI ΣΔ A/D converters

49. A technique to reduce the impact of hysterisys in ΣΔ analog to digital converters

50. A 65nm CMOS EDGE/UMTS/WLAN tri-mode four-channel time-interleaved ΣΔ ADC