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This paper introduces the design of low noise amplifier, using for ultra-low frequency. There′s a new loop in the paper, formed by a low-pass transconductance and a self-cascode MOSFET, proposed to stabilize the output bias voltage of the amplifier. By using the loop with the constant transconductance bias circuit, the open-loop gain of the amplifier is constant at about 40 dB. It does not vary with the supply voltage, process and temperature. In the amplifier, a self-cascode MOSFET is used as a gain unit to enable the amplifier output range to reach rail to rail, with the use of full differential current bias. This amplifier has a remarkable in-band high-power supply rejection ratio, up to 101.4 dB. The power ripple has almost no effect on the output signal, when the wearable devices are powered by high impedance sources.

This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process. The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0.8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.

In order to improve the regulation capability of the wide range output voltage and light load efficiency, this paper proposed two level control strategy. Asymmetrical Pulse Width Modulation(APWM) was used in the LLC series resonance with voltage double rectifier and a feedback controller was added to get the proper crossover frequency and enough relative stability. Phase-locked loop control(PLL) was used to track the resonant frequency. In addition, considering the high switching frequency of the secondary leakage inductance will affect the input and output voltage gain, this paper added secondary leakage inductance to the model to reduce the reverse blocking voltage of rectifier diode, which can improve the accuracy of modeling. Simulation and experiment have verified the correctness of the theoretical analysis and the feasibility of the control strategy.

As GLOBALFOUNDRIES continues design in 7 nm technology for high speed Serdes IP, it should be noted that the complexity of layout design has increased. New challenges include complex DRC verification and complex MPT methodology in the design flow. It is therefore important to develop a layout flow(addressing this challenge), which includes new features of EDA tools (always important to the design). For example: Cadence Virtuoso Interactive Physical Verification System(VIPVS). This enables real time sign-off quality DRC checks, shortens the layout verification loop, and delivers rapid means for MPT coloring(a highlight of VIPVS). This paper will show how the GLOBALFOUNDRIES high speed Serdes layout team is using VIPVS(for rapid DRC checks and MPT coloring) in a high speed Serdes project designed in GLOBALFOUNDRIES 7 nm Finfet technology. The paper will include the verification flow and feature highlights, as well as usage of newly embedded VIPVS features.

In order to meet the requirement of high stability frequency source when DRFM(Digital Radio Frequency Memory) system collects external input signals, a design method of multi-channel, low phase noise synchronous frequency source based on two-stage PLL is proposed in this paper. Six channels of arbitrary frequency signal output in the range of 2.26～2 600 MHz are realized. Through the method of linear superposition, the phase noise model of PLL is analyzed theoretically, and the optimal design is carried out according to the source of phase noise. Finally, the spurious and phase noise of the frequency source circuit are tested. The test results show that the spurious suppression is better than -60 dBc and the phase noise suppression is better than-104.91 dBc/Hz@500kHz when the frequency source circuit outputs 1.25 GHz frequency.

Based on the ISO/IEC 18000-6C standard protocol, this paper conducted research on the design and implementation of UHF RFID tag′s physical layer baseband circuit. According to the design requirements and indicators of the baseband specified in the standard protocol, SystemVerilog was used to model the tag sending and receiving basebands, and the theoretical derivation and design implementation of the key modules in the baseband were given. SystemVerilog, as a hardware description and verification language developed on the basis of Verilog, can greatly improve the efficiency of SoC design. Finally, Modelsim SE-64 10.4 was used to simulate the digital baseband circuit design of the tag. The results showed that the digital baseband met the requirements of ISO/IEC 18000-6C protocol. This design provides a design reference for single-chip UHF RFID tag.

In order to enhance the performances of clock and data recovery circuit(CDR) in the high speed multichannel serial transceiver system, a novel phase interpolator(PI) circuit used in CDR has been proposed in the paper. It adopts four groups of differential signal and DAC to act on common load resistance, generates complementary thermometer code through digital filter to control DAC output current, realizes phase weight allocation for differential input clock to make 128 times interpolated, and optimizes the differential signal by input stage four phase correction circuit and duty cycle adjustment circuit. This chip is fabricated in 40 nm CMOS process, the simulation results show that PI has good linearity from 1 GHz to 6 GHz, and DNL is no more than 1.4 LSB, INL is no more than 1.5 LSB, and has been successfully applied to a variety of high speed SerDes.

This paper is aimed at researching and designing LDOs without off-chip capacitors. Whether the LDO can stabilize the output voltage when there is no external capacitor is studied. Based on this, a new type of high-stability LDO structure with no off-chip capacitor is studied to apply power to the internal circuit module in the DC-DC converter. The poles of the LDO are adjustd by adjusting the internal op amp structure and Miller compensation of the op amp. The simulation results show that the structure has high stability and can output a stable voltage.

This paper presents a rail-to-rail constant transconductance operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-gm by using dummy input differential pairs. The problem which causes total gm variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower gm variation. The gm of this Op Amp′s input stage varies around ±2%.

To make power electronic devices miniaturization and lightweight, GaN FET is paid extensive attention in power electronic application fields because of its advanced performance than Si device. GaN FET structure and its driving circuit have important impacts on operating safely and stably. In the paper, firstly, the GaN FET structure and its products are introduced; Secondly, the isolated method is described, then the principles of the discrete driving circuit and the integrated driving circuit are presented; Finally, GaN FET′s application is summarized.

The received signal amplitude of zero-IF Doppler radar usually has a large dynamic range, and this large dynamic range brings inconvenience to signal acquisition. In view of the large dynamic range of this received signal, this paper designs a signal conditioning circuit from the perspective of negative feedback, which includes low noise amplification module, automatic gain control module, non-diode precision rectifier module and subtraction amplifier circuit module; it realizes the function of automatic gain control. After the computer software is simulated, the hardware circuit is fabricated, and the function of the debugging circuit meets the requirements.

This paper presents a novel all-digital phase-locked loop with variable phase accumulator circuit structure. The design of the system is completed by using EDA technology, and the system simulation experiment is carried out by using ModelSim software, and the hardware experiment is carried out. The experimental results show that the all-digital PLL with variable phase accumulator can extend the phase-locked range of the system loop, increase the frequency of PLL,reduce the total power consumption of the system, and do not increase the logic resources in the FPGA chip. Because the internal signal of the PLL is transmitted in parallel,the speed of PLL can be greatly improved. The PLL can be embedded into an electronic system chip as a functional module, and can be widely used in communication, electronic measurement and automatic control.

In this paper, the current development status and bottleneck problems of terahertz science and technology are presented. The emphasis of discussion is on research progress of the core component in terahertz circuits, monolithic integrated power amplifier. According to the kinds of base material in integrated circuit(IC) design, compound including InP and GaAs terahertz amplifier IC are compared with those made by silicon including bulk CMOS and SiGe. Basing on this category standard by material, the performances of terahertz amplifier IC are analyzed and concluded in the aspects of circuit topology and specifications.

This paper proposed a technique of maximum efficiency and constant voltage output for wireless power transfer system. A semi-bridge rectifier is used to replace the common diode rectifier on the receiver side, and a Boost circuit is adopted to regulate the system output voltage. The duty cycles of the semi-bridge rectifier and the Boost circuit are online adjusted so that the wireless power transfer system can keep both maximum efficiency and constant voltage output when load varies and mutual inductance of coupled coils changes. Experimental results verified the feasibility of the proposed technique and the correctness of the theoretical analysis.

Large size and thick oxide transistors are usually used in the design of Low Dropout Linear Regulator(LDO) in order to increase the upper limited voltage of input supply voltage，but this will increase the area of the circuit. In order to solve this problem, this paper proposed a wide range voltage stabilizing circuit based on an improved Wilson current mirror structure, which provides power and bias for LDO. The simulation results show that the external supply voltage range from 3.5 V to 6 V can be converted to 1.8 V supply voltage, so that the LDO core circuit can still use 0.18 μm MOS transistors under the high input supply voltage, which can reduce the chip area. And it can bring convenience to the design of LDO analog module.

Traditional way of FPGA configuration file update is using development tools to write FPGA target code to storage devices such as Nor Flash through the JTAG way.However,when the system becomes complicated with multiple FPGA,it takes a long time to update all the FPGA due to the limitation that the JTAG way can only update FPGA once a time. Therefore this paper proposes a FPGA online updating method,which can update multiple FPGA programs at the same time, greatly shorten the update time and reduce the cost of the system.

This paper proposes a new series-L/parallel-tuned class DE-1 power amplifier. The theoretical analysis was conducted according to zero current switching(ZCS) and zero current slope switching(ZCSS) conditions. The closed form design equations under ideal switching conditions were given. The performance of the power amplifier was calculated. Theoretically, class DE-1 power amplifier has efficiency of 100%. It has both of the advantage of class D and class E-1. Circuit implementation was carried out to verify the proposed amplifier. In the experiment, the supply voltage is 3 V, and the optimal working frequency is 110 kHz, and the power amplifier achieves efficiency of 97.8%. Good agreement between theory and experiment results is achieved.

In this paper, a high-voltage gain DC/DC converter with the output capacitors connected in series is proposed, which makes up for the insufficiencies that the voltage gains of existing converters are affected seriously by the parasitic parameters; the output capacitors withstand high voltage stresses that equal to the output voltage. All the capacitors and the input source in the proposed converter are connected in series to supply the load, thus, reducing the capacitors′ voltage stresses. Higher voltage gain can be obtained by the extended converter. The operational principles and calculating methods of relevant parameters are presented, based on which, the simulation and experiment are conducted. The results verify the feasibility of the proposed converter.

Aiming at the problems of complex supply voltage and high sensitivity of power in ADC for the industrial Internet of Things, this paper presents a flexible, low power and low noise reference voltage generator for the SAR ADC to obtain good PSRR and a stable supply-independent full-scale range. The 2.5 V or 1.5 V is available based on the different range of supply voltage(2.65 V～3.6 V or 2.2 V～3.6 V). This circuit support off-chip capacitor to provide transient current for the ADC to avoid the power-hungry integrated buffer in series sampling mode. An energy-efficient mode which uses integrated buffer rather than off-chip capacitor can be configured to obtain short setting time to save energy during each one-shot sample. Testing result shows the circuit can save power/energy with no loss in ADC performance.

This paper based on the efficiency of UVM verification methodology,and combined with the characteristics of UVM reusability.In order to verify the function of baseband RF interface circuit,it need build hierarchical modular verification platform.The verification analysis show that baseband RF interface hardware circuit framework can be transplanted to UVM environment,which not only code coverage and functional coverage can be increased,but also the efficiency of verification can be substantially improved. At the same time,the hardware RTL is constrained by DC,which the area of receiving path of RF interface circuit is 0.3 mm2 and power consumption is 39 mW can be obtained. The area of transmission path of RF interface circuit is 0.5 mm2 and power consumption is 58 mW can be obtained.

This paper uses internal matching technology and the cell structure of a single cell to design and implement a design of 3.8～4.2 GHz power amplifier. The amplifier is based on a GaN HEMT independently developed by Nanjing Electronic Device Institute. By optimizing the design, the amplifier achieves a peak output power of Pout greater than 30 W and the PAE of the amplifier greater than 48%, at a relative bandwidth of 10%, a drain-source voltage of 28 V, and a continuous wave operating condition,which fully shows the GaN power device′s broadband, high-efficiency, and high-power performance,so the device has broad prospects for engineering applications.

Car charger is the key equipment for the development of electric vehicles. Such equipment is prone to exceed the maximum temperature rising limitation when operating in high temperature environment. Meanwhile, the device temperature of the vehicle equipment is difficult to obtain directly due to the road conditions and other issues, and therefore cannot achieve the temperature protection. In this paper, a smart power adjustment method based on the power device lumped parameter thermal circuit model is proposed aimed at overcoming this problem. In this method, the power device that has the highest temperature inside the charger is analyzed firstly. Then, power device lumped parameter thermal circuit model is established, which is correlated with the ambient temperature and output power. Next, the optimal model parameters can be effectively estimated via the least square method. The experimental results verify that the power control method based on the thermal path model can effectively limit the temperature rising of the charger power device, and improve the thermal stability of the charger.