Sensitive amplifier design for high speed interface JESD204B

This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process. The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0.8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.