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We propose a method to track signals from quadrant photodiodes (QPDs) in heterodyne laser interferometers that employ digital phase-locked loops for phase readout. Instead of separately tracking the four segments from the QPD and then combining the results into length and differential-wavefront-sensing signals, this method employs a set of coupled tracking loops that operate directly on the combined length and angular signals. The benefits are an increased signal-to-noise ratio in the loops and the possibility of adapting the loop bandwidths to the differing dynamical behavior of the signals being tracked, which now correspond to physically meaningful observables. We demonstrate an improvement of up to 6 dB over single-segment tracking, which makes this scheme an attractive solution for applications in precision intersatellite laser interferometry in ultralow light conditions. © 2020 authors.

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode., Electronics

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode., Electronics