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A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA., QC 20100525

A new technique for realizing CMOS digitally controlled decibel-linear variable gain amplifier (VGA) circuits is described. CMOS VGA circuits employing the proposed technique are then given. Besides being effective and simple to use from a system point of view, the VGA circuits offer a stable gain characteristic with precise gain control that is achievable without component spreading, The VGA provides a 25 dB gain control range per stage, with 0.55-dB gain steps and a gain error of less than 0.5 dB. It can also be digitally reconfigured to give a 60-dB gain control range with 6-dB gain steps. The VGA circuit provides digital offset trimming, processes voltage or current input signals and operates in a fully differential configuration. Simulation and experimental results are provided., QC 20100525

A technique for designing digitally programmable CMOS integrated filters for multi-standard wireless receivers is presented. The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 mu m chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards., QC 20100525

The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 mu m CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented., QC 20100525