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Cellular Automata (CAs), a ubiquitous computational tool proposed by John von Neumann, illustrate how great complexity emerges from simple rules of dynamical transitions between space and time interconnected simplistic entities. CAs perform as mathematical computation models, but also they are a powerful medium to model nature and natural systems. As a computational platform, CAs come with unified memory and computation in the same physical area, attributed as a strong candidate against the limitations of data transfer, known as the von Neumann bottleneck. On the other hand, Memristors with their inherent Computing-In-Memory compatibility, can be easily considered as appropriate nanoelectronic devices to be coupled with CAs towards an energy and time efficient computational paradigm. In particular, CA present a vast area of applications, comprising various NP-complete hard to be solved problems arriving from computer science field, like the well-known Shortest Path, Bin Packing, Knapsack and Max-clique problems, as well as physical, chemical and biological processes and phenomena, such as epileptic seizures in relation with healthy and pathogenic brain regions and, moreover, real life applications like pseudorandom number generation and simplistic, but with highly complex behavior, models like the famous Game of Life. The outcome of employing Memristors in CAs applications is promising in terms of parallelization, power consumption, scalability, reconfigurability, and high computing performance., QC 20230921

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Ion irradiation induced interface mixing was used to generate silicon nanocrystals at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications, photoluminescence as well as electroluminescence. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose as well as annealing temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 10^6 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention. The photoluminescence of the ion irradiated MOS structure gives a profile in the red region which is typical for Si nanocrystals. Preliminary results about the electroluminescence caused by an applied ac voltage will be reported too.

Ion irradiation induced interface mixing was used to generate silicon nanocrystals at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications, photoluminescence as well as electroluminescence. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose as well as annealing temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 10^6 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention. The photoluminescence of the ion irradiated MOS structure gives a profile in the red region which is typical for Si nanocrystals. Preliminary results about the electroluminescence caused by an applied ac voltage will be reported too.

In this communication, we report on the realization of low-temperature processed Electrically Erasable Programmable Read-Only Memory (EEPROM) like device with embedded gold nanoparticles. The realization is based on the fabrication of a V-groove SiGe Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400 degrees C. The electrical characteristics of the final hybrid Metal Insulator Semiconductor FET (MISFET) memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented., QC 20111004. Conference: 31st International Conference on Micro- and Nano-Engineerin. Vienna, AUSTRIA Date: SEP 19-22, 2005

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

A process scheme for the fabrication of a low temperature SiGe V-groove MOSFET is demonstrated. The transfer and output characteristics show promising results for the device performance. The source/drain resistance and the quality of the gate insulator/SiGe channel must be optimized for device operation improvement., QC 20111012. 0th International Conference on Micro and Nano Engineering. Rotterdam, NETHERLANDS. SEP 19-22, 2004

In silicon nanocrystal (nc) based metal-oxide-semiconductor (MOS) memory structures a fine control of the Si nc location in the gate oxide is required for the pinpointing of optimal device architectures. In this work, we show how to manipulate and control the depth-position, size and surface density of two dimensional (2D) arrays of Si ncs embedded in thin (<10 nm) SiO2 layers, fabricated by ultra-low-energy (typically 1 keV) ion implantation and subsequent annealing. Particular emphasis is placed upon the influence of implantation and annealing conditions and oxide thickness on the nanocrystal characteristics (e.g. size, density) and the charge storage properties of associated MOS structures. Structural investigation is performed by using specific characterization methods including Fresnel imaging for the measurement of the injection distance between the substrate and the nc band, as well as spatially resolved Electron Energy Loss Spectroscopy using the spectrum-imaging mode of a Scanning Transmission Electron Microscope to evaluate the size distribution and density of the ncs.

iIon irradiation induced interface mixing was used to generate silicon nanoclusters at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose and post-irradiation temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 106 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention and ensure the standard 10-year retention time needed for true non-volatile memory applications.

An abstract is not available, please contact the authors.

iIon irradiation induced interface mixing was used to generate silicon nanoclusters at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose and post-irradiation temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 106 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention and ensure the standard 10-year retention time needed for true non-volatile memory applications.

An abstract is not available, please contact the authors.

iIon irradiation induced interface mixing was used to generate silicon nanoclusters at the SiO2-Si interface of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications. No particular processing issues have been encountered during integration of this technique in standard submicronic C-MOS technology. The memory properties of the fabricated structures as a function of the Si+-irradiation dose and post-irradiation temperature and time have been examined through electrical measurements of capacitors and transistors. Low-voltage operating devices that can endure more than 106 programming/erasing cycles have been successfully achieved. While excellent device uniformity and reproducibility have been observed over 6-inch wafers, more research is still required to improve charge retention and ensure the standard 10-year retention time needed for true non-volatile memory applications.

In silicon nanocrystal based metal–oxide–semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the ‘‘injection distance’’ can be achieved by varying the Si1 ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy ~XTEM! method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values ~2 nm! can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM are compared with Monte-Carlo simulations of the implanted Si profiles taking into account dynamic target changes due to ion implantation, ion erosion, and ion beam mixing. This combination of experimental and theoretical studies gives a safe explanation regarding the unique technological route of obtaining Si nanocrystals at distances smaller than 5 nm from the channel: the formation of nanocrystals requires that the interface mixing due to collisional damage does not overlap with the range profile to the extent that there is no more a local maximum of Si excess buried in the SiO2 layer.

An abstract is not available, please contact the authors.

An abstract is not available, please contact the authors.