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Atomic layer deposition of Al:ZrO(2) films on In(0.53)Ga(0.47)As substrates is shown to be a promising route to boost the oxide permittivity with respect to Al(2)O(3) gate dielectrics and concomitantly take benefit from the reducing effect of the trimethylaluminum precursor on the In(0.53)Ga(0.47)As surface. We demonstrates that increasing the number of initial Al(2)O(3) cycles in the growth sequence can improve the physical quality and the electrical response of the Al:ZrO(2)/In(0.53)Ga(0.47)As interface while preserving the overall composition of the oxide. (C) 2011 The Japan Society of Applied Physics

In this letter, we propose an atmospheric pressure-chemical vapor deposition technique to grow metastable GeSn epitaxial layers on Ge. We report the growth of defect free fully strained undoped and in-situ B doped GeSn layers on Ge substrates with Sit contents up to 8%. Those metastable layers stay fully strained after 30 min anneal in N-2 at 500 degrees C.; Ge-Sn interdiffusion is seen at 500 degrees C but not at lower temperature. B is 100% active in the in-situ GeSn:B layers up to a concentration of 1.7 x 10(19) cm(-3). GeSn:B provides slightly lower Hall hole mobility values than in pure p-type Ge especially for low B concentrations. (C) 2011 American Institute of Physics [doi.10.1063/1.3645620]

In this letter, we propose an atmospheric pressure-chemical vapor deposition technique to grow metastable GeSn epitaxial layers on Ge. We report the growth of defect free fully strained undoped and in-situ B doped GeSn layers on Ge substrates with Sit contents up to 8%. Those metastable layers stay fully strained after 30 min anneal in N-2 at 500 degrees C.; Ge-Sn interdiffusion is seen at 500 degrees C but not at lower temperature. B is 100% active in the in-situ GeSn:B layers up to a concentration of 1.7 x 10(19) cm(-3). GeSn:B provides slightly lower Hall hole mobility values than in pure p-type Ge especially for low B concentrations. (C) 2011 American Institute of Physics [doi.10.1063/1.3645620]

A good dielectric layer on the GaAs substrate is one of the critical issues to be solved for introducing GaAs as a candidate to replace Si in semiconductor processing. In literature, promising results have been shown for Al2O 3on GaAs substrates. Therefore, atomic layer deposition (ALD) of Al2O3has been studied on GaAs substrates. We have been investigating the influence of the ALD process (thermal vs plasma-enhanced ALD) as well as the influence of the starting surface (no clean vs partial removal of the native oxide). Ellipsometry and total X-ray reflection fluorescence were applied to study the growth of the ALD layers. Angle-resolved X-ray photoelectron spectroscopy was used to determine the composition of the interlayer. Both processes were shown to be roughly independent of the starting surface with a minor dependence for the thermal ALD. Thermally deposited ALD layers exhibited better electrical characteristics based on capacitance measurements. This could be linked to the thinner interlayer observed for thermally deposited Al2 O3. However, the Fermi level was not unpinned in all cases, suggesting that more work needs to be done for passivating the interface between GaAs and the high- k layer. © 2009 The Electrochemical Society.

A good dielectric layer on the GaAs substrate is one of the critical issues to be solved for introducing GaAs as a candidate to replace Si in semiconductor processing. In literature, promising results have been shown for Al2O 3on GaAs substrates. Therefore, atomic layer deposition (ALD) of Al2O3has been studied on GaAs substrates. We have been investigating the influence of the ALD process (thermal vs plasma-enhanced ALD) as well as the influence of the starting surface (no clean vs partial removal of the native oxide). Ellipsometry and total X-ray reflection fluorescence were applied to study the growth of the ALD layers. Angle-resolved X-ray photoelectron spectroscopy was used to determine the composition of the interlayer. Both processes were shown to be roughly independent of the starting surface with a minor dependence for the thermal ALD. Thermally deposited ALD layers exhibited better electrical characteristics based on capacitance measurements. This could be linked to the thinner interlayer observed for thermally deposited Al2 O3. However, the Fermi level was not unpinned in all cases, suggesting that more work needs to be done for passivating the interface between GaAs and the high- k layer. © 2009 The Electrochemical Society.

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage (C-V) measurements are necessary for GaAs metal-oxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2, and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage (C-V) measurements are necessary for GaAs metal-oxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2, and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied At. Layer Deposition (ALD) of high-k dielec. layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidn. in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidn. states lower than 4+. Still, elec. results indicate that small amts. of Ge in oxidn. states lower than 4+ are not detrimental for device performance. Partial intermixing was obsd. for high-k dielec. and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates. [on SciFinder (R)]

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied At. Layer Deposition (ALD) of high-k dielec. layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidn. in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidn. states lower than 4+. Still, elec. results indicate that small amts. of Ge in oxidn. states lower than 4+ are not detrimental for device performance. Partial intermixing was obsd. for high-k dielec. and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates. [on SciFinder (R)]

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage (C-V) measurements are necessary for GaAs metal-oxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2, and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage (C-V) measurements are necessary for GaAs metal-oxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2, and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.

Hydrogen ion implantation is conventionally used to initiate the transfer of Si thin layers onto Si wafers coated with thermal oxide. In this work, we studied the feasibility of using plasma hydrogenation to replace high dose H implantation for layer transfer. Boron ion implantation was used to introduce H -trapping centers into Si wafers to illustrate the idea. Instead of the widely recognized interactions between boron and hydrogen atoms, this study showed that lattice damage, i.e., dangling bonds, traps H atoms and can lead to surface blistering during hydrogenation or upon postannealing at higher temperature. The B implantation and subsequent processes control the uniformity of H trapping and the trap depths. While the trap centers were introduced by B implantation in this study, there are many other means to do the same without implantation. Our results suggest an innovative way to achieve high quality transfer of Si layers without H implantation at high energies and high doses. © 2005 American Institute of Physics.

The formation of a thin strained Si layer on top of a strain-relaxed SiGe buffer is a recent approach to improve the drive current of complementary metal-oxide-semiconductor devices by inducing strain within the transistor channel. At the same time, advanced process technologies require junction formation processes with minimal diffusion and very high dopant activation. Solid-phase epitaxial regrowth is a low temperature process based on preamorphization and subsequent regrowth leading to highly activated and shallow junctions. In this letter, we investigate the stability of the thin strained Si layer, during solid-phase epitaxial regrowth process by monitoring the Ge redistribution/strain after the preamorphization step (without any anneal) and after the thermal regrowth process.

Hydrogen ion implantation is conventionally used to initiate the transfer of Si thin layers onto Si wafers coated with thermal oxide. In this work, we studied the feasibility of using plasma hydrogenation to replace high dose H implantation for layer transfer. Boron ion implantation was used to introduce H -trapping centers into Si wafers to illustrate the idea. Instead of the widely recognized interactions between boron and hydrogen atoms, this study showed that lattice damage, i.e., dangling bonds, traps H atoms and can lead to surface blistering during hydrogenation or upon postannealing at higher temperature. The B implantation and subsequent processes control the uniformity of H trapping and the trap depths. While the trap centers were introduced by B implantation in this study, there are many other means to do the same without implantation. Our results suggest an innovative way to achieve high quality transfer of Si layers without H implantation at high energies and high doses. © 2005 American Institute of Physics.

Applied Sciences

Applied Sciences

A low-temperature electrical characterization of ultrathin oxide MOS capacitors with p(+) poly-Si1-xGex and poly-Si gate is performed. The investigated structures are suitable for future nano-scaled high speed MOSFETs. The aim of this study is to compare the low-temperature performance of poly-Si1-xGex and poly-Si gate MOS structures in the nanoscale channel length regime. Apart from the significant change in the flat band voltage, the result shows that all the poly-Si and poly-Si1-xGex gated MOS structures exhibit two centres of polarity change (zero-temperature coefficients) in capacitance. The second polarity change leads to an exclusive phenomenon in these structures. The low-temperature capacitance is found to be less than high-temperature capacitance at strong accumulation and this is in contrast to what has been observed so far in metal-gated capacitors. It is also observed that the temperature dependence of the tunnelling current is only on the oxide thickness and not on the gate material used.

CoxTi1-x layers were deposited on Si (100) and on Si/Si80Ge20 (100) capped with 30- or 40-nm-thick Si at 650 degreesC substrate temperature at 1x10(-6) Pa pressure. The Co-silicide films grown by reactive deposition epitaxy were characterized by Rutherford backscattering-channeling, x-ray difraction, by depth profile analysis of the components, and by sheet resistance measurements. The Ti content of the deposited Co layers was between 0.1 and 8 at. %. The epitaxy of the layers on Si and on Si/Si80Ge20 improved by increasing the Ti concentration. The minimum yield of the channeling and the full width at half maximum value of the rocking curve of CoSi2 decreased. The sheet resisitance of the formed layers was also minimal in these cases. The method applied is promising to form epitaxial CoSi2 layers on SixGe1-x substrates.

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