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Aiming at the problem of poor image contrast and loss of visual information on electrowetting electronic paper display， this paper proposes an image hierarchical mapping technique based on human visual system. Firstly, the image is decomposed into the base layer and the detail layer, and the brightness of the base layer is enhanced. Then, the enhanced image is partitioned by Weber-Fechner law to realize the partition logarithmic mapping, and weighted and merged with the detail layer as the output image. At the same time, in order to achieve precise modulation of the electrowetting display, the brightness is local linearly stretched. The experimental results show that compared with traditional mapping methods, the entropy value of the algorithm in this paper is closer to the original map, the PSNR,SSIM and UIQI values of image evaluation index are respectively improved by 0.2~0.6，0.07~0.4 and 0.1~0.6. The method makes the relationship between the corrected voltage and brightness more linear, increases the image details on the electrowetting electronic paper, improves the contrast, and the overall visual effect is better.

Wi-Fi6 standard will be major Wi-Fi technology dominated for deployment after 2020. But to support increasing bandwidth requirements and number of access devices per year, Wi-Fi technology and throughput still need to be further developed and improved. This paper will introduce the key technology involved for latest IEEE802.11be standard discussion, describing the major changes on physical and MAC layer, particularly providing the analysis for multi-access point coordination, hybrid automatic repeat request and Wi-Fi full duplex mode. Finally, this paper will introduce the granted progress of latest 6 GHz applied by both new 802.11ax version and 802.11be with related Wi-Fi function impact.

With the wide application of reconfigurable design technology in the field of cryptography, the existing reconfigurable cryptography system can hardly meet the needs of high-speed communication and equipment miniaturization.Therefore, it is the goal of this paper to design a high performance reconfigurable processing architecture that can flexibly implement block cipher algorithms.Based on the reconfigurable array structure and the multi-launch mechanism, this paper proposes a reconfigurable multi-launch pipeline processing architecture to solve the problems of low throughput and low resource utilization of the reconfigurable cryptography system.This architecture is able to transmit multiple packets in parallel and pipeline processing, and has higher throughput and unit utilization, which greatly improves the algorithm performance of the reconfigurable system.Experiments show that the throughput of AES can reach 3.19 Gb/s under the operating frequency of 350 MHz.Compared with the single-launch structure, its performance improved by about 1.1 times.

The solar photovoltaic industry has developed rapidly in recent years. Accurate diagnosis of the location and type of PV module faults can improve the efficiency of operation and maintenance personnel. In this paper, a deep learning diagnostic model based on convolutional neural networks-long short term memory(CNN-LSTM) is proposed, which can be used to complete the detection task. In this paper, a fault classification method based on current performance is established. The algorithm firstly designs a feature extraction algorithm based on the layout characteristics of the PV array, and extracts the lateral and vertical features of the PV array current to obtain the spatial and temporal characteristics. The CNN network further extracts the lateral features and compresses the vertical features to solve the problem of single feature types and slow training. Finally, the LSTM neural network is used to complete the fault diagnosis of the PV modules.

Because the designed frequency band of Geosynchronous synthetic aperture radar(GEO SAR) satellite signal possibly shares or overlaps with the frequency band of various Global Navigation Satellite System(GNSS) signals which have been put into use, the ground GNSS receiver may be subject to the pulse radio frequency interference generated by GEO SAR signal. In order to evaluate the influence of GEO SAR signal on the performance of GNSS ground receiver, a parametric theoretical model based on International Telecommunication Union(ITU) related standards is proposed in this paper. The model uses the "source-path-receiver" analysis method to extract parameters from the three aspects of GEO SAR signal, signal propagation path and receiver model for interference evaluation. Then, according to ITU standards, the influence of high-orbit SAR signal as additive pulse radio frequency interference on the performance of GNSS receiver is evaluated. Taking the representative B3I signal as an example, this paper evaluates the performance of different types of B3I receivers for GEO SAR signal under the condition of the assumed design parameters. The results show that the performance of the receiver decreases slightly in the presence of high-orbit SAR signal interference, but it can still work normally.

In this paper we introduce an electronic seal base on 13.56 MHz RFID technology. The seal includes national commercial encryption algorithm SM7 to ensure the reliability and security. The radio frequency identification also allows the seal to be easily managed. In this paper we also introduce architecture of this kind of seal which include the antenna structure, function module, state machine working flow, 3 pass authentication and so on. Finally we realize a chip on HJEE110nm standard CMOS technology, the chip core only occupies 0.5 mm2 and the power consumptions are less than 100 μA. The chip packaged in ID1 completely matches the standard of ISO14443 and ISO10373-6, and chip packaged in seals in three specifications works perfect with the encrypt reader.

This paper proposes a three-dimensional Logistic-Sine cascade map(3D-LSCM). Firstly, a three-dimensional Logistic-Sine cascade map was constructed by using the output of the Logistic map as the input of the Sine map. Secondly，this paper designs an image encryption scheme using 3D-LSCM, which consists of two rounds of scrambling and two-way diffusion，and introduces the plaintext as part of initial conditions of 3D-LSCM to enchance the difficulty in deciphering equivalent keys. The feasibility of the algorithm was confirmed throung security analysis and numerical simulation.

In this paper, the digital beamforming algorithm for horizontally polarized directional antenna array in narrowband multipath environment is studied. Because the steering vector of directional antenna arrays is complex and cannot be modeled exactly, blind beamforming algorithm is usually used for directional antenna arrays. As the existing blind beamforming algorithms require much prior information, work poorly for weak signals, have limited applications, and need high computational complexity, this paper designs a multi-polarization heterogeneous array cooperative processing scheme, and proposes a new multipath strengthening beamforming algorithm based on adaptive loading projection. The heterogeneous array consists of vertical polarization omnidirectional antenna array and horizontal polarization directional antenna array. The new algorithm utilizes the respective advantages of the two polarization arrays. This algorithm combines the methods of spatial smoothing, sampling matrix inversion, and spatial projection, and further improves the robustness of waveform estimation through adaptive loading processing. The algorithm requires less computation and less prior information, and has strong adaptability to non-ideal conditions. The implementation process and error analysis of the new algorithm are deduced, and effectiveness of the new algorithm is verified through computer simulations.

Through comparison, algorithm optimization, pipeline accelerated design and structural compatibility extension of a large number of mainstream algorithm, this paper propose an algorithm that is good for modulo operation structure compatibility: improved radix-4 interleaved modular multiplication algorithm. It has advantages of short path and simple structure, and has advantages in compatibility design, can achieve full flow accelerated operation, and achieve the high speed and reconfigurable design purposes. The improved radix-4 interleaved modular multiplication unit proposed in this paper can directly realize plus-minus module division and modular addition without adding extra structure, which solves the problem of the waste of independent resources. The unified modular unit is synthesized under the 65 nm CMOS process. The area is 0.117 mm2. The clock frequency is 526 MHz. A 576 bit modular multiplication and modular division are completed at 0.55 μs and 2.98 μs respectively.

The purpose of this paper is to use genetic algorithm(GA) to process image with bottom noise, and the processing effect is improved through the improvement of GA. Combining with image segmentation, this paper expounds the working mechanism of GA and the design methods of main modules such as fitness calculation, selection, crossover and mutation, and gives the specific values of parameter setting. The key issues such as the relationship between generation gap and excellent individuals, the substitution relationship between individual among different generations, the selection method of intersection points and the selection of mutation positions, and the maintenance of population number are clarified. The image with bottom noise is processed by this algorithm, the results show that the target image can be separated from the background with noise by GA, but the processing time is 7.416 seconds. In order to improve the processing efficiency, the traditional algorithm is improved by adaptively adjusting the crossover probability and mutation probability of the population using evolutionary generation and individual fitness values. The same noise image is segmented by improved GA. The results show that the improved GA has better image segmentation effect, the processing time is only 0.751 seconds, the efficiency is improved by nearly 10 times.

With the development of science and technology, ultrasonic scalpel is widely used in medical treatment. In practical application, in order to make the transducer of the ultrasonic scalpel convert electrical energy into mechanical energy as much as possible, this paper uses parallel impedance matching to realize the impedance matching of the ultrasonic scalpel, which makes the transducer of the ultrasonic scalpel present pure impedance, thus maximizing the output power of the transducer and reducing the transmission of the transducer. Heat has increased the service life. In addition, the parameters of the transducer of the ultrasonic scalpel will change with temperature and environment in the course of using. Therefore, this paper designs a frequency tracking method for the resonant frequency of the transducer, which tracks the phase difference between current and voltage, and then sends it to the FPGA for calculation. A phase difference is obtained. When the phase deviation occurs, a frequency conversion formula is used to adjust the output frequency, so as to achieve the effect of frequency tracking. Through practical verification, the impedance matching and frequency tracking method of the ultrasonic scalpel designed in this paper can achieve the automatic frequency tracking under different loads, and run reliably.

Large-dimensional matrix multiplication is often implemented by submatrix block method. The maximum size of the submatrix determines the speed of the entire matrix multiplication. Concerning the problem that the matrix size directly processed by the classical systolic structure is severely limited by the IO bandwidth, this paper proposes a large-dimensional matrix chain multiplier structure with extremely low IO bandwidth requirements, and completes the hardware design implementation and performance verification. The following is the main work of this thesis. Firstly, optimizing the data organization of matrix multiplication, realizing the input matrix size has nothing to do with IO bandwidth, and make maximum use of the internal logic and storage resources of the device. Secondly, according to the optimized data organization form, the chain multiplier hardware is designed for realizing the source data calculation and transmission overlap operation. Thirdly, the adaptability of the multiplier to the matrix scale is enhanced, and the designed chain multiplier can be configured in real time as multiple independent chains, multiple sets of operations in parallel. Lastly, completing the hardware implementation and performance test of chain multipliers of different sizes on the Xilinx C7V2000T FPGA chip. On this chip, the chain multiplier proposed in this paper supports up to 800 arithmetic units, which is 8 times the size of the classic systolic structure. In the same number of operators, the chain multiplier performance proposed in this paper uses only the classical pulsation structure to calculate the IO bandwidth of 1/8 to obtain equal performance.

This paper interprets the evolution route of network service capability provided by telecom operators in traditional Internet of Vehicles industry chain. On the basis of the development trend of future Internet of Vehicles and intelligent transportation, this paper explains the growth bottlenecks and capacity challenges faced by traditional channel service, and analyses the service capability improvement brought by 5G key technologies such as edge computing and network slicing with Internet of Vehicles. This paper also explores the innovation of Internet of Vehicles service mode and business mode that operators can carry out.

Quartz vibrating beam accelerometer expresses acceleration in the form of frequency output. In the inertial navigation system, it is necessary to convert the frequency value into an acceleration value and then perform attitude calculation. Using software method for floating point calculation requires a lot of computing power of CPU. In order to optimize the calculation speed of frequency conversion, the paper designs a floating-point calculation acceleration unit for frequency conversion applications, which is implemented and verified based on FPGA. The results show that the system from data sampling to frequency conversion, then converts the frequency value into acceleration for the attitude calculation. The angular velocity measured by the gyroscope is integrated, and finally the data fusion is completed. Using the floating-point acceleration unit designed in the paper to achieve frequency conversion, the speed is improved by 2 times.

In this paper, the development trend of intelligent transport system(ITS) and the state art of vehicle-road collaboration are introduced. This paper focuses on the cloud-network-edge-terminal architecture of vehicle-road collaboration, includes central cloud, transport private network/telecommunication network, edge cloud, vehicle/road-side terminal and their collaborations.The open framework of information service capability of multi-source data fusion based on cloud-network-edge-terminal architecture for vehicle-road collaboration is presented. The specific functional requirements, API invocation methods and protocols are discussed in detail.

In order to satisfy the high-performance and low-power dissipation requirement in wireless communication, this paper proposes a low storage capacity and low-power dissipation Turbo decoder architecture based on the reverse recalculation and linear estimation by changing the storage method of the forward state metric, while the FPGA implementation structure is given. The results show that compared with the existing Turbo code decoder, the decoding structure designed in this paper reduces the storage capacity to 65%, and the decoding performance is close to the Log-MAP algorithm. In particular, compared with the traditional decoder architecture, dynamic storage capacity power dissipation is reduced by about 50%, and the overall power dissipation of the decoder architecture is decreased by 4.97%, 8.78%, 11.93%, 14.18% and 14.65% at the frequency of 25 MHz,50 MHz,75 MHz,100 MHz and 125 MHz, respectively.

The increasing functionality and complexity of electronic systems places higher demands on the efficiency of system verification tests. The traditional satellite test platform is customized according to the specific model task. Its design and development cycle is long, and the comprehensive cost is difficult to adapt to the current task requirements. To this end, this paper proposes a general simulation test platform architecture for on-board solid-state storage controller based on System Verilog. It uses a hierarchical model internally, and the signal interface uses APB bus standard uniformly. It can be configured by testing the platform data source and format to adapt to onboard solid-state storage controllers of different capacities, different rates and different configurations. Experiments show that the test platform designed in this paper has certain versatility, which can effectively save test time and improve test coverage compared with traditional test platform.

The computer technology related to unmanned vehicle driving is developing rapidly, and the vehicle identification technology is more and more widely used in intelligent traffic monitoring and intelligent traffic information systems. Vehicle identification includes sports vehicle detection, type classification, vehicle tracking and so on. In this paper, the key technologies such as vehicle identification detection in smart car unmanned technology are deeply explored. Using the image recognition result of the vehicle, this paper chooses the CAM offset algorithm based on the average color difference value as the basis for identification. The algorithm uses the vehicle color as the feature to perform the tracking detection method, and does not follow the light and dark of the vehicle. The shape change is disturbed, and the reliability in the vehicle identification process is high. This algorithm is improved to achieve better recognition of the vehicle.

A miniaturization research of rocket upper stage electric load management center(EMLC) based on SIP concept is presented in this paper, in the background of electron-integrated system on rocket, focusing on the method of design and implementation of a SIP control system in EMLC. The architecture design of SIP control system is completed with the mixed analog-digital FPGA as hardware platform. A design and implementation method of IPs like main protocol engine core, warm backup fiber optic Ethernet core and other main function core has been elaborated. An assistance health management(AHM) system′s design and implementation method in this paper has been simply illustrated. The simulation result of EMLC and experiment result of the SIP control system are also been given.

This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process. The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0.8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.

Based on the TensorFlow framework, this paper builds convolutional neural networks to recognize the defects in the electroluminescent images of cells. It selects the exposed data set that contains the different types of defects in the cell. Based on the traditional VGGNet network, the full convolution neural network is used for training, and this paper analyzes the training effects of different loss functions and dropout probabilities on data set. Experiments have shown that the algorithm accurately recognizes whether the cell is defective. The study also shows that the compression network structure greatly increases the training rate of the algorithm, which makes the simplified model more portable and provides an effective solution for a wide range of real-time defect recognition.

With the development of computer technology, fire image processing technology combining computer vision, machine learning, deep learning and other technologies has been widely studied and applied. Aiming at the complex preprocessing process and high false positive rate of traditional image processing methods, this paper proposes a method based on deep convolutional neural network model for fire detection, which reduces complex preprocessing links and integrates the whole fire identification process into one single depth neural network for easy training and optimization. In view of the problem of fire detection caused by similar fire scenes in the identification process, this paper uses the motion characteristics of fire to innovatively propose the combination of fire frame position changes before and after the fire video to eliminate the interference of lights and other similar fire scenes. After comparing many open learning open source frameworks, this paper chooses Caffe framework for training and testing. The experimental results show that the method realizes the recognition and localization of fire images. This method is suitable for different fire scenarios and has good generalization ability and anti-interference ability.

With the rapid development of Internet applications and the rapid growth of users , the reviews and opinions of stock market largely reflect the quotation of the stock market,simultaneously it affects the ups and downs of the stock market. Therefore, how to quickly and efficiently analyze the attitudes and opinions of netizens to the stock market,which,this question plays important role in guiding us to predict the stock market. The thesis studies the rising and falling trend of stocks by analyzing the emotional polarity of different professional issuing stocks. This paper proposes a sentiment analysis method based on a dictionary of consistent integrated financial phrases and weighted at the end of paragraph, which can solve the dependency problem of sentiment dictionary on the domain，and it can effectively improve the accuracy of sentiment analysis. In addition, this paper also proposed a windowed stock prediction model, which can be used to analyze the optimal value of the forecast event window. The experimental results shows that it will be better to predict the rising or falling trend of a particular stock just based on the stock market sentiment analysis.

5G Ultra-Dense Network(UDN) allows a large number of high-density low-power transmission points(TPs) to be deployed in heterogeneous networks(HetNets). It greatly improves the system performance whereas introduces inter-cell interference(ICI). To eliminate ICI, CoMP concept has been widely used in UDN. But it also brings new challenges, how to effectively allocate network resources is one of them. This paper proposes a CLA-CoMP algorithm to improve both the rate of the small cell edge users and the system sum rate. In order to deal with the power allocation problem in UDN, this paper adopts P2UPA strategy, which aims to allocate higher power to users with the high probability of association. Simulation results reveal that jointly use CLA-CoMP and P2UPA can significantly improve the system performance, compared with the case of average power allocation.

Unified power flow controller(UPFC) is the most advance flexible ac transmission system(FACTS). Active/reactive power balance for UPFC is analyzed in this paper when it is working in power flow control mode, and an improved real time power coordinate control strategy is proposed in paper. In the parallel converter control loops, an improved real-time dynamic feed forward method is added to reduce over voltage caused by imbalance power. The results of hardware-in-loop simulation based RT-LAB platform show that this new coordinate control strategy，comparing with the conventional one, can decrease excessive voltage excursions of the send terminal ac voltage and DC-link voltage and improve the control performance during power flow changing or system occurring fault.

The defect area located by Faster R-CNN has weak edges. The area would be over-segmented or under-segmented if conventional segmentation algorithm is adopted. This paper made an analysis on precise threshold segmentation algorithm for workpiece defects based on Faster R-CNN location, reconstructing the localization area by morphological opening and closing reconstruction algorithm, processing the reconstructed image by Otsu′s dual threshold method, segmenting transformed images by maximum entropy threshold segmentation method, and finally measuring the area, perimeter and other parameters of the segmented defects. The research shows that the algorithm in this paper has higher segmentation ability regarding workpiece defects(crack, bubble and slag), compared to conventional algorithms. It not only can accurately segment objects with weak edges, but also can effectively remove the interference from the contour background to the segmentation.

Current residual current action protection device cannot detect the type of residual current in the electric shock current. In this paper, an electric shock test platform is built and the residual current data is obtained by experiment. Based on the above data, this paper presents a residual current classification method based on the AdaBoost algorithm, which firstly obtains the characteristic components of different types of residual current components, and then maps these component features to the AdaBoost algorithm. The type of electric shock current in total residual current is detected by AdaBoost algorithm. Compared with SVM and random forests, the results show that the proposed method has some advantages, which can provide theoretical basis and support for the development of the subsequent adaptive residual current action protection device.

In the current anti-jamming communication, the spread spectrum communication has been studied deeply with the advantages of strong anti-jamming ability and good security performance. In this paper, the code index modulation and multi-ary spread spectrum technology are analyzed and compared. Code index modulation technology is based on the development of direct sequence spread spectrum, in the transmitter information bits are mapped to the pseudo noise(PN) code index and the modulation symbol respectively. The in-phase and orthogonal parts of the modulation symbol select PN codes activated to spread spectrum, and then transmitted through an antenna. The difference between multi-ary spread spectrum technology and code index modulation technology is that the multi-ary spread spectrum technology does not have modulation symbols, and only sends out the activated spread spectrum code through the antenna. This paper will introduce the basic models, spread spectrum gain analysis and complexity analysis of the two kinds of spread spectrum technology. The simulation results show that the code index modulation system has higher spectral efficiency and anti-interference ability.

Vehicular Ad hoc Networks(VANETs) have special characteristics on the highway, such as high speed，low density, scarce communication infrastructure, and low vehicle connectivity. These characters make it difficult for vehicles on the highway to access to other vehicles or Road Side Units(RSUs). This paper presents a model which implements fog computing in highway service areas to assist vehicles in acquiring content of interest. In this Vehicle Fog Computing(VFC) model, the highway service area collects various services provided by vehicles from various places, and uses a large number of parked vehicles and slow-moving vehicles as fog devices. Localized forwarding through VFC not only reduces communication latency, but also achieves satisfactory content access and real-time data streaming. Moreover, this paper formulates the relationship between communication energy consumption and system delay, then uses the Outer Approximation(OA) algorithm to optimize its trade-off in fog computing. The simulation results show that the communication delay of the system will be significantly reduced with the increase of energy consumption by using the communication mode and equalization optimization algorithm combined with fog computing and cloud computing.

This paper studies the precoder design in multi-input multi-output(MIMO) interference channels, where it is assumed that interference channels have line-of-sight(LOS) paths and can be modeled as Rice fading channels，and the transmitter can only retrieve channel statistical information—channel mean matrices. Based on maximum signal-to-interference-plus-noise ratio(SINR) and signal-to-interference-plus-noise difference(SIND) criteria, two precoding methods are proposed. For the first method, an auxiliary variable is introduced so that the original non-convex problem is transformed into a convex one. Consequently, this problem is solved by the proposed bisection method that incorporates convex optimization softwares. For the second method, the original problem is decomposed into several sub-problems and the corresponding analytical solution is derived. By computer simulation, this paper demonstrates the convergence of the proposed algorithm and analyzes the effect of Rice factor on the system performance. The proposed methods are compared with a few classical transmission schemes and the results show the superiority of the proposed methods.

In order to improve the regulation capability of the wide range output voltage and light load efficiency, this paper proposed two level control strategy. Asymmetrical Pulse Width Modulation(APWM) was used in the LLC series resonance with voltage double rectifier and a feedback controller was added to get the proper crossover frequency and enough relative stability. Phase-locked loop control(PLL) was used to track the resonant frequency. In addition, considering the high switching frequency of the secondary leakage inductance will affect the input and output voltage gain, this paper added secondary leakage inductance to the model to reduce the reverse blocking voltage of rectifier diode, which can improve the accuracy of modeling. Simulation and experiment have verified the correctness of the theoretical analysis and the feasibility of the control strategy.

Based on the traditional first-order compensation bandgap reference analysis, this paper proposes a novel high-order compensation technique and uses this technique to design a curvature compensation voltage reference with a low temperature coefficient over a wide temperature range. The circuit structure proposed in this paper is designed and simulated based on the VIS 0.15 μm BCD technology. The simulation results show that the average output voltage of the reference circuit is 539 mV and the temperature coefficient is 1.40 ppm/℃ in the wide temperature range(-60 ℃~120 ℃), the line regulation of output voltage at 27 ℃ is 0.001 9% under the power supply from 1.3 V to 2.1 V, and the power supply rejection is greater than 84 dB at 100 Hz.

The real-time and accurate automatic detection technology of road surface damage has important significance for highway management and maintenance. This paper combines the FPGA-based pavement damage detection system to research the positioning accuracy. Due to the influence of factors such as the installation perspective of the system equipment and the speed of the carrier, the accuracy of the road surface positioning may be reduced. This paper proposes a pavement damage location algorithm based on machine vision distance compensation. The experimental results show that when the vehicle′s driving speed is below 72 km/h, the positioning error is reduced from 5 m to 2 m. It meets the requirements of the system design.

There is a problem of poor load regulation in traditional LED power supply. In this paper, a control strategy of inductor current compensation based on the output voltage feedback is used to compensate the output current deviation caused by the load adjustment with the load voltage signal. In this paper, the factors affecting the load regulation of Buck constant current topological are analyzed theoretically. Combined with analysis of engineering application data, the control strategy of load regulation is optimized. Finally, the control method is verified on a LED power supply of 200 watts. The load regulation rate was reduced from 0.03%/V to 0.01%/V, which verified the correctness of the control methodproposed and achieved the effect of optimizing the load regulation rate.

This paper presents a new type of power supply for information network. This scheme has adopted a new topology which can transmit electric energy bidirectional underwater. This function can realize both energy storage and external charging. In this paper, the compensating circuit has been confirmed based on the practical application condition, then the influence of the working frequency to the system has been analyzed, the influence of the eddy current loss in sea water environment has been analyzed and vivificated. At last the experiment of the wireless charging undersea has been completed. This paper has realized 83% of the transfer efficiency when the transmission distance is 15 cm. The result can achieve the technical indicator and verify the feasibility and effectiveness of the proposed strategy.

This paper propose a finger vein recognition algorithm based on the CapsNets(Capsule Network for short) to solve the problem of the information loss of the finger vein in the Convolution Neural Network(CNN). The CapsNets is transferred from the bottom to the high level in the form of capsule in the whole learning process, so that the multidimensional characteristics of the finger vein are encapsulated in the form of vector, and the features will be preserved in the network, but not in the network after the loss is recovered. In this paper, 60 000 images are used as training set, and 10 000 images are used as test set. The experimental results show that the network structure features of CapsNets are more obvious than that of CNN, the accuracy of VGG is increased by 13.6%, and the value of loss converges to 0.01.

This paper presents a non-orthogonal multiple access(NOMA) relay method which is based on mmWave wireless heterogeneous system and can support Internet of things(IoT) applications. The scheme takes advantage of the deployment specialty of low power relays，together with energy harvesting capabilities of IoT devices，so that it can infer the performance of UEs with relay collaboration. With the help of a relay or IoT device, the downstream NOMA transmission consists of two phases.(1)The base station(BS) transmits the composite signal to the user equipment(UE) and the selected relay device simultaneously by applying the NOMA. (2)The BS sends another signal to the UE 1 while the relay device transmits the signal to the UE 2. The simulation results show that the method designed in this paper is feasible and effective.

In this paper, the design method and application process of a Board Support Package(BSP) based on the Zynq-7000 All Programmable SoC(AP SoC) is implemented. The BSP design is mainly for the field of industrial automated monitoring. It provides an effective implementation process of embedded system BSP, which is beneficial to improve the development efficiency of industrial automated monitoring system. In this paper, In view of the industrial monitoring equipment that uses serial communication mode, the FPGA engineering for small automatic monitoring system is designed, and the embedded Linux system is built by PetaLinux tools, which are designed specifically for FPGA-based SoC. Finally, the correctness and stability of the BSP design are verified with the self-developed hardware platform based on Zynq XC7Z010 series model chip.

In engineering application, when dealing with fuzzy images,due to the way of space deconvolution is more difficult, the frequency domain transformation of the image is usually processed and implemented in the frequency domain.In the light of the frequency domain processing of image deblurring system has such problems as large consumption of hardware resources, poor flexibility of conversion and long processing time, etc. Based on the DE2 development board as the hardware platform, combined with the characteristics of fuzzy image and deblurring algorithm, this paper designs and implements a frequency domain processing method for image deblurring system by means of input data preprocessing, in situ calculation, throwing position, pipeline structure and parallel processing. The experimental data show that the accuracy of the method in the frequency domain processing of the image data is kept above 98%, and the hardware resources only use 9 162 logical units. The experimental results show that the system designed in this paper is superior to other similar systems in processing precision and resource utilization.

In this paper, according to the characteristics of reconfigurable high speed serial bus(UM-BUS), a new architecture of intelligent wheelchair system based on UM-BUS is proposed, which is superior to the traditional architecture in scalability and dynamic fault tolerance. Based on the new architecture, a common hardware and software platform is designed. The intelligent wheelchair control system designed in this paper has the characteristics of easy expansion, high reliability and versatility.

In order to ensure the reliability, stability and high transmission rate of fifth-generation mobile communication technology(5G), this paper proposes a hybrid check matrix construction algorithm based on iterative coding algorithm with linear coding complexity. Firstly, this paper improves the traditional iterative coding algorithm and makes it suitable for non-binary low density parity check(NB-LDPC) codes. Then it adopts backward iterative method to change the coding scheme and the structure of the check matrix so that the progressive edge growth(PEG) algorithm has a lower triangular structure and uses it as the base matrix. Finally, a QC-LDPC algorithm with a lower triangular structure is used to generate a cyclic shift matrix and a finite field coefficient matrix. At the same time, the effect of the short loop is eliminated, and an optimal check matrix is selected from the algorithm. Simulation results show that the non-binary LDPC code constructed by the hybrid construction algorithm not only has linear coding and storage complexity, but also has strong error correction capability.

Aiming at the problem of low sampling rate and poor portability in the current signal acquisition system, this paper designs a signal acquisition system with high speed and strong portability based on FPGA. Firstly, FPGA samples the signal at a high speed through controlling the ADC. And then，the data is stored in the NAND Flash by using the DMA(Direct Memory Access) mode. Finally, the signal stored in the NAND Flash chip could be demonstrated live by using the LCD. Paper begins with describing the overall design framework of the system. Then, it introduces the hardware design and the implementation, followed by the outcome produced by the experiment that the signal acquisition system samples the ultrasonic signal. The experiment results show that the system could carry on a long-time and multi batch data acquisition stably at relatively high sampling rate.

This paper proposes a feature matching algorithm for partial limitation search regions, which combines spatial constraints with local descriptors. Based on the ASIFT algorithm, this paper improves the defects of directly removing one-to-many and many-to-one feature points in the feature matching phase. Since many of these removed feature points can be properly matched,resulting match points less. This paper will find a new unmatched pair of points within the surrounding area of the matching pairs, and finally achieve the goal of raising the correct number of matches. Experiments show that the feature matching algorithm proposed in this paper can greatly increase the number of feature matching compared with the ASIFT algorithm.

This paper describes a fast verification full-chain co-simulation flow based on the VSDP-XcitePI for extracting on-chip power supply models and simulating the effects of on-chip coupling interference. With this flow, XcitePI extracts the RLCK model or S-parameter model for metal layers of on-die power network and signals. This chip-level model together with package model was used in creating a new system-aware test bench to analyze the digital-to-analog interference in a RF AFE IC. The simulation results match well with the test phenomenon. Chip area of the IC used in analysis is 1.44 mm2, the analysis accuracy could support 10 μV variation，and the analysis bandwidth exceeds 5 GHz. In addition. This paper also introduces the flexible S-parameter post-processing flow inside VSDP platform, which ensures the convergence and high efficiency for the full-chain simulation.

MBIST(Memory Built-In Self-Test) technology has extensive application in the memory test. In view of the traditional BIST controller register transfer level description language design process is relatively complicated, special flexibility EDA tools to define algorithm flexibility is poor, and the circuit structure is fixed, this paper proposes the use of high-level synthesis tools BIST controller design method. This paper takes SRAM as the object, describes the MARCH algorithm in C language, and uses port allocation, pipeline optimization and array segmentation to optimize the design. Finally, with the tools of the FPGA platform it verifies and evaluates the function reliability and scle controllability of the high-level synthesis synthesized RTL code level circuit. Compared with the two traditional methods, the limitation of algorithm implementation and circuit structure is eliminated, and the implementation period of the algorithm is reduced.

High performance data converter is the core device of the fifth generation mobile communication base station system. Its sampling rate is no less than 3 GS/s and the resolution is higher than 12 bit. Therefore, it is inevitable for high-speed serial interface to replace traditional interface circuits. Based on JESD204B protocol, this paper designs a high speed serial interface control layer circuit applied to 3 GS/s 12 bit ADCs. Under the premise of ensuring high-speed transmission, it considers the power consumption and resources in the compromise. The circuit adopts the pre-frequency technique to complete the framing in the transmission layer, and the 8 B/10 B coding is implemented by using the polar information to simplify encoding techniques in the data link layer. In Vivado 16.1 environment, using the Xilinx ZC706 FPGA PHY IP and JESD204B Receiver IP, the verification of the interface circuit proposed in this paper is completed. The experimental results show that the data transmission is correct, the serialized transmission speed is 7.5 Gb/s. Compared with the same type interface design, the transmission speed is increased by 50%.

Aiming at the difficulty of Beidou reflected signal acquisition, this paper presents a capture algorithm for the reflected signal in the Beidou GNSS-R receiver. The algorithm uses the navigation data in the direct signal to peel off the navigation data in the reflected signal, and improves the traditional reflection signal acquisition algorithm through the cyclic accumulation operation and the FFT correlation.The algorithm can greatly reduce the computational complexity and shorten the capture time of long time integral of the reflected signal.In this paper, the MATLAB simulation of the new algorithm is carried out, and compared with the traditional coherent-uncoupling algorithm and the difference coherence algorithm. The simulation results show that the algorithm in this paper is superior to the traditional coherent noncoherent and differential coherent acquisition algorithm in capturing performance.

The use of discontinuous reception(DRX) mechanism is an important means for the mobile terminal to reduce power consumption. In the NB-IoT system, the business has characteristics of low rate and low frequency,it requires the terminal to have very low power consumption. To meet its business characteristics, this paper has made some changes to DRX, and the extended discontinuous reception(eDRX) is adopted. In this paper, the basic principle of the eDRX mechanism is analyzed in detail by various timer operations, furthermore, the eDRX model is built. The simulation results show the performance of eDRX mechanism in power saving and delay.

The design goals of VANET(Vehicular Ad-Hoc Networks) are to provide an open public road safety services，and to improve the comfort and efficiency of driving. In VANET, multi channels are employed to transmit safety information and non-safety information respectively. This paper analyzes protocols associating with VANET in detail and proposes an improved multi-channel MAC cooperation scheme. Based on the network simulation software NS2, this paper designs the simulation model for VANET, adds the multi-channel module and application layer module into the network simulation software NS2, and then simulates the single channel and multi-channel, and the improved MAC protocol. From the simulation, it shows that compared with the single channel, multi channels can obtain better throughput, and the improved MAC protocol also has lower latency and message collision ratio than the original standard.

For high performance CPU design, especially on 16 nm and advanced process nodes, with the increase in the number of signoff corner, increasing the clock common path, improving the clock latency correlation on various RC corners, decreasing local skew of design, those are our common view. The Cadence innovus Flexible H-tree(FlexHtree) feature not only provides the symmetric buffer structure and equal wire lengths benefits of an H-tree, but also relaxes the requirement to be geometrically symmetric, enabling clock tree synthesis even in floorplans with sink placement. This paper presents an automatic Flexible H-tree flow to decrease clock skew on different corners. Meanwhile, this paper will discuss the impact of multi-taps counts and synthesis engines of the sub-tree on clock skew and design timing in details, then choses a better solution. Finally, in terms of timing, power consumption, and instance counts results, the design mentioned in this paper is suitable to use Flexible H-tree clock structure in comparison to CCOPT and fishbone structure clock tree.