Osburn, C.M., Kim, I., Han, S.K., De, I., Yee, K.F., Gannavaram, S., Lee, S.J., Lee, C.-H., Luo, Z.J., Zhu, W., Hauser, J.R., Kwong, D.-L., Lucovsky, G., Ma, T.P., and Ozturk, M.C.
The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure Si[O.sub.2] in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)--for example, Hf[O.sub.2], Zr[O.sub.2], and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (~[10.sup.5] A/[cm.sup.2]). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.