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This article presents a novel space vector pulsewidth modulation (SVPWM) for a three-phase binary-cascaded multilevel inverter (BCMLI). The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This article proposes a further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the BCMLI and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with the line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experimental results of a BCMLI are presented to verify the effectiveness of the proposed technique.

Abstract In this paper, a 1‐kW DC‐DC buck converter with a four‐phase interleaved matrix inductor is proposed for battery charging applications. It is well‐known that the DC bias on the inductor will cause high core loss as it changes the B–H characteristic. Typically, the transient conduction mode employed in high voltage applications for zero‐voltage‐switching of devices would cause higher inductor current ripple. The conventional approach to reduce the effect of DC bias and inductor current ripple is employing multi‐phases. However, the cost and size of the converter will increase significantly. This paper proposes the matrix inductor which has a small volume and reduces the effect of the DC bias by flux sharing and flux cancellation at the same time, results in low inductor core loss. With the interleaved operations the output current ripple can be lower which is suitable for battery charging application. Besides, the comparison of the synchronous and interleaved operation is presented. A 1‐kW prototype is built and the experimental results show that the peak efficiency is 99.1% and 99.2% for synchronous and interleaved control, respectively. Additionally, the output current ripple of the interleaved operation is reduced by 85% in comparison with the synchronous operation.

The increasing usage of LLC-type dc-dc converters in utility, automotive, and power distribution applications has led to a push for a further increase in the converter's operating load range and efficiency. The secondary-side rectifier remains one of the lossiest areas in the converter, alluring designers to synchronous rectification (SR). One method is drain-source SR for cyclically adaptive, closed loop SR. However, when utilized, a severe current oscillation can be observed. An increase in SR duty cycle results in an increase in conduction time of the SR channel over the body diode. This issue becomes increasingly prevalent due to the usage of wide band-gap MOSFETs with high reverse drops and low sensed signal strength. This results in a current oscillation effect, leading to inconsistent SR operation, output ripple, and high EMI. In this paper, the issue is root caused analyzed. A method of improving drain-source SR for light-load SR operation is proposed. The method is prototyped on an FPGA to alleviate the issue on a 600-Vin/340-Vout 2.5-kW LLC-DCX (DC transformer) power converter.

Coupled-inductor buck converters are more effective in high step-down applications compared to conventional buck converters given the same circuit complexity. A coupled-inductor buck converter can adopt synchronous conduction mode to fully mitigate turn-on loss and operate at high frequency. However, this typically induces large circulating currents and harms the converter's light-load efficiency. To alleviate these issues, this paper analyzes the mechanisms behind synchronous conduction mode and then proposes a dual-loop control method solution. The variable-frequency outer loop of the proposed control minimizes conduction and deadtime loss, while the voltage-mode-controlled inner loop provides the necessary output voltage regulation. Experiments are conducted with a compact prototype converter using switching frequencies higher than 2 MHz, and the prototype is verified under load transients to validate both control loops. The results show that the light-load efficiency can be boosted by more than 8%.

In this paper, a controller design methodology is proposed for a CLLLC-type bidirectional resonant converter. The soft switching of all devices in this topology and the very high operating frequency lead to increased overall system efficiency. However, the dynamic nature of this converter is highly dependent on loading conditions, which proves challenging when designing the voltage and current closed-loop controllers. System instability is mainly due to the high-Q resonant peaking, which is observed in the open-loop bode-plots. In this paper, the controller design methodology is proposed, which accounts for the dynamics behavior due to load variations. The controller stability will be evaluated against the entire range of operating switching frequency. Both battery charging and regeneration modes will be described and analyzed. The focal contribution of this paper will focus on defining the worst operating scenarios for the converter using system-level modeling and analysis. In addition, the controller will be defined based on these operating points. To validate and verify the controller design methodology proposed, a 3.5-kW converter is designed with the appropriate output voltage and current loop controllers. The step response verified a stable system designed and thus proving the proposed controller design methodology.

This paper proposes a galvanically isolated dc-dc converter that can regulate the input voltage in a wide range. It is based on the series resonance dc-dc converter (SRC) topology and a novel boost rectifier. The proposed topology has a smaller number of semiconductors than its SRC-based existing topologies employing an ac-switch in the boost rectifier. The proposed dc-dc converter comprises only two diodes and one switch at the output side, while the existing solutions use two switches and two diodes to step up the voltage. The proposed converter boosts the input voltage within a single boosting interval in the positive half-cycle of the switching period. In addition, the resonant current in the negative half-cycle is sinusoidal, which could enhance the converter efficiency. The resonant capacitor voltage is clamped at the level of the output voltage. Therefore, the voltage stress of the capacitor could significantly reduce at various input voltage and power levels. This makes it perfect for distributed generation applications such as photovoltaics with wide variations of input voltage and power. The converter operates at the fixed switching frequency close to the resonance frequency to obtain the maximum efficiency at the nominal input voltage. The zero-voltage switching (ZVS) feature is achieved in the primary semiconductors, while the diodes in the output-side rectifier turn off at nearly zero current switching. The mathematical model and design guidelines of the proposed converter are discussed in the paper. The experimental results confirmed the theoretical analysis based on a 300 W prototype. The maximum efficiency of the converter was 96.8% at the nominal input voltage, and the converter has achieved a wider input voltage regulation range than that with the boosting cell comprising an ac-switch.