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Herein, cryogenic field‐effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide‐channel interfaces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investigated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X‐Ray absorption spectroscopy at total fluorescence (XAS‐TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple SiO2$\left(\text{SiO}\right)_{2}$ coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible. [ABSTRACT FROM AUTHOR]

Neuromorphic computing employs a great number of artificial synapses which transfer information between neurons. Conventional two‐ or three‐terminal artificial synapses with homosynaptic plasticity suffer from a positive feedback loop problem. Synapses with heterosynaptic plasticity are thus required to perform learning, processing and modulating simultaneously. Here, complementary metal‐oxide‐semiconductor compatible artificial synapses based on ferroelectric polarization modulated Schottky diodes (FEMOD) on silicon, which enables heterosynaptic plasticity with multi‐functionalities, high endurance, low power consumption, and high speed, are presented. High accuracy is obtained in the supervised learning simulation of artificial neural networks due to the large number of conductance states, good linearity, and small variations of FEMOD synapses. Boolean functions are demonstrated with only one or two FEMOD devices operating at low voltage and low power consumption. The proposed device structure performs multi‐functions of biological synapse and Boolean logic, thus provides high potential for the future large scale and low power neuromorphic computing applications. [ABSTRACT FROM AUTHOR]

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SSth of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance Gm at 5.5 K. [ABSTRACT FROM AUTHOR]

Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor's key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity. [ABSTRACT FROM AUTHOR]

In this article, vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top–down approach are demonstrated. Thanks to optimized dry etching and digital etching, high-performance Ge GAA nanowire pFETs show low subthreshold swing (SS) of 66 mV/dec, small DIBL, and ION/IOFF ratio of > 106. The impact of nanowire diameter scaling from 65 to 20 nm on the key electrical figures of merit (FOMs) of vertical nanowire devices is investigated. The devices with 65-nm diameters show the highest ION and peak transconductance Gmax due to reduced total resistance Rtot, while the smallest diameter devices yield the largest ION/IOFF ratios and the smallest DIBL due to strong gate electrostatics. The source/–drain asymmetry inherently exists in the vertical nanowire architectures. By swapping the source and drain, electrical FOMs keep the similar trend in diameter scaling. ION, Rtot, and Gmax asymmetry can be attributed to top–bottom contact resistance difference resulting from the doping deactivation effect in small nanowires. [ABSTRACT FROM AUTHOR]

We present a systematic study on the effects of CF4 plasma immersion ion implantation (PIII) in Si on the phase evolution of ultra-thin Ni silicides. For 3 nm Ni, NiSi2 was formed on Si substrates with and without CF4 PIII at temperature as low as 400 °C. For 6 nm Ni, NiSi was formed on pure Si, while epitaxial NiSi2 was obtained on CF4 PIII Si. The incorporation of C and F atoms in the thin epitaxial NiSi2 significantly reduces the layer resistivity. Increasing the Ni thickness to 8 nm results in the formation of NiSi, where the thermal stability of NiSi, the NiSi/Si interface and Schottky contacts are significantly improved with CF4 PIII. We suggest that the interface energy is lowered by the F and C dopants present in the layer and at the interface, leading to phase evolution of the thin Ni silicide. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$. The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$. Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors. [ABSTRACT FROM AUTHOR]

This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter. [ABSTRACT FROM AUTHOR]

Deals with a study which compared experimental longitudinal damage straggling and lateral damage spread induced by 1.0 high energy Cu[sup+] in silicon(100) with the transport of ions in matter prediction. Experimental details; Results and discussion.

Presents a study which examined the lateral spread effects in the implantation of Ar[sup+], Xe[sup+], and Hg[sup+] ions in Si³N[sup4] films. Experimental details; Results and discussion; Conclusion.

Proposes a concept called ion beam defect engineering. Background to the study; Experimental procedures; Experimental results.

Presents a study which examined the depth distribution of mercury ions implanted in potassium titanyl phosphate. Experimental details; Results and discussion; Conclusion.

Presents a study on xenon ions at energies from 50 to 500 keV that have been implanted into the polymer ladderlike polyphenylsilsesquioxane. Experimental procedures; Results and discussion; Agreement found between the experimental data and calculated values for the mean projected range.

Studies the gettering effects of ion-beam defect engineering in BF[sub2]-implanted silicon. Details on the experiment; Results of the study; Conclusion.

The subthreshold behavior of floating-gate MOSFETs connected with ferroelectric capacitors (FeCs) was investigated experimentally and theoretically. We found that the subthreshold swing (SS) decreases with decreasing ferroelectric capacitance (i.e., with the decreasing FeC area), in contrast to the voltage dividing effect of regular dielectric capacitors. The ferroelectric polarization switching counteracts the effect of voltage dividing by introducing an additional charge onto the floating gate, which improves the SS and leads to the observed SS dependence. The SS improvement caused by the polarization switching is different from the negative capacitance effect, which is helpful to further understand the ferroelectric transistor. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance. [ABSTRACT FROM AUTHOR]

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a non-hysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade. [ABSTRACT FROM AUTHOR]

This letter presents an experimental capacitance–voltage C – V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance C\textsf {gs} to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance C\textsf {gd} at higher V\textsf {ds} and Vg . Comparable values of C\textsf {gs} and C\textsf {gd} would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations. [ABSTRACT FROM PUBLISHER]

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I – V and G – V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: gm/{I}\text {d} , gm/gds , fT and fT/{I}d{V}d , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40~\text V^-1 , for currents lower than 10 nA/ \mu \textm ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ \mu \textm . [ABSTRACT FROM PUBLISHER]

Presents a study which iInvestigated lateral straggling of xenon ions in potassium titanyl phosphate. Details on the experiment; Results of the study; Conclusion.

Presents a study on the distributions of implanted iron ions into both amorphized quartz crystal and silicon at energies by using the Rutherford backscatteting technique. Experimental procedures; Results and discussion.

We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance–voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of C\mathrm {gs} to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance C\mathrm {gd} . This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits. [ABSTRACT FROM PUBLISHER]

This paper provides an experimental proof that both the ON-current I\mathrm{\scriptscriptstyle ON} and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use of a selective and self-adjusted silicidation, thus enlarging the area for band-to-band-tunneling (BTBT) in a region directly underneath the gate. In addition, a counter-doped pocket within the SiGe layer at the source tunnel junction is introduced in order to sharpen the corresponding doping profile and, consequently, to shorten the resulting tunneling length. Experimental analysis of activation energies Ea identifies BTBT, dominating the drain current Id in the SiGe/Si heterostructure TFET over a wide region of the gate voltage Vg , thus reducing parasitic influence of Shockley–Read–Hall recombination and trap-assisted tunneling. Both a relatively high I\mathrm{\scriptscriptstyle ON} = 6.7\mu \text{A}/\mu \text{m} at a supply voltage V\mathrm{ DD} = 0.5 V and an average SS of about 80 mV/decade over four orders of magnitude of Id were achieved. [ABSTRACT FROM AUTHOR]

We present a method to form ultrathin highly uniform Ni(Al) germanosilicide layers on compressively strained Si1-xGex substrates and their structural characteristics. The uniform Ni(Al) germanosilicide film is formed with Ni/Al alloy at an optimized temperature of 400 °C with an optimized Al atomic content of 20 at. %. We find only two kinds of grains in the layer. Both grains show orthogonal relationship with modified B8 type phase. The growth plane is identified to be {10-10}-type plane. After germanosilicidation the strain in the rest Si1-xGex layer is conserved, which provides a great advantage for device application. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the enhancement-mode (E-mode) LaLuO3 (LLO)-AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) fabricated using fluorine (F) plasma ion implantation with a gate-dielectric-first planar process. The E-mode MIS-HEMTs exhibit a threshold voltage (VTH) of 0.6 V, a peak transconductance of \sim193~mS/mm, a small hysteresis of 0.04 V in linear region characterized by a pulse-mode current-voltage measurement, and significantly suppressed current collapse under high-drain-bias switching conditions. X-ray photoelectron spectroscopy and secondary ion mass spectrometry analyses manifest that the negatively charged F ions penetrating into the (Al)GaN barrier layer serve as the primary VTH modulation mechanism, whereas the F ions in the fluorinated LLO film form chemical bonds with La/Lu atoms and become charge-neutral. The suppressed current collapse is verified as an advantageous byproduct of the F plasma ion implantation that also fluorinated the SiNx sidewalls in the vicinity of the gate electrode, and therefore, suppress electron injection to the gate-drain access region. [ABSTRACT FROM AUTHOR]

Terbium scandate (TbScO3) and lanthanum scandate (\LaScO3) have been investigated as gate dielectrics for metal–oxide–semiconductor field-effect transistors on both silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. X-ray photoelectron spectroscopy analysis revealed the presence of a silicate at the interface for \TbScO3 on Si, whereas a silicate/\SiO2-like interface was found for the \LaScO3 on Si. A full replacement gate process was developed to fabricate high-\kappa/metal gate fully depleted transistors on SOI and sSOI. \LaScO3 transistors with a gate length of 2 \mu \m show excellent characteristics with steep subthreshold slopes of 72 mV/dec, high Ion/Ioff ratios, and electron mobility of 180 \cm^2/\V \cdot \s for SOI and 375 \cm^2/\V \cdot \s for sSOI at low field, which is superior to corresponding \TbScO3 devices. All sSOI transistors showed 2 times higher electron mobility than SOI reference devices. [ABSTRACT FROM PUBLISHER]

In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with \(p\) -doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and \(n\) -doped Si drain. We observe a linear relation of gate length, L \(_{\mathrm {\mathbf {g}}}\) , and ON-current, I \(_{\mathrm {{ON}}}\) , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation. [ABSTRACT FROM AUTHOR]

Alloy scattering in a sSi/Si0.5Ge0.5/strained Silicon on Insulator (SOI) (sSOI) quantum-well (QW) p-MOSFET is investigated by hole density modulation through applying back-gate biases. The hole mobility under negative back-gate biases is found degraded by intensified alloy scattering at low electrical field because more holes are distributed in the bulk Si0.5Ge0.5. At higher electrical field, the higher density of holes populated at the Si/Si0.5Ge0.5.interface and less holes in the bulk Si0.5Ge0.5.result in less pronounced alloy scattering, leading to mobility enhancement under negative back-gate biases. This confirms experimentally that alloy scattering does not play a significant role in the hole mobility of sSi/Si0.5Ge0.5/sSOI QW p-MOSFETs under normal operating mode. [ABSTRACT FROM PUBLISHER]

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications. [ABSTRACT FROM AUTHOR]

A high-\kappa\ \LaLuO3 (LLO) thin film is successfully incorporated into AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) as the gate dielectric. The LLO–AlGaN/GaN MISHEMTs fabricated with a planar process exhibit a high ION/IOFF of \10^9, a maximum drain current of 820 mA/mm at VGS = 3\ \V, a peak transconductance (Gm) of \sim192 mS/mm, and a steep subthreshold slope (SS) of \sim73 mV/dec. [ABSTRACT FROM PUBLISHER]

We report the study of high-dielectric-constant (high-κ) dielectric LaLuO3 (LLO) thin film that is grown on AlGaN/GaN heterostructure by molecular beam deposition (MBD). The physical properties of LLO on AlGaN/GaN heterostrucure have been investigated with atomic force microscopy, x-ray photoelectron spectroscopy, and TEM. It is revealed that the MBD-grown 16 nm-thick LLO film is polycrystalline with a thin (∼2 nm) amorphous transition layer at the LLO/GaN interface. The bandgap of LLO is derived as 5.3 ± 0.04 eV from O1s energy loss spectrum. Capacitance-voltage (C-V) characteristics of a Ni-Au/LLO/III-nitride metal-insulator-semiconductor diode exhibit small frequency dispersion (<2%) and reveal a high effective dielectric constant of ∼28 for the LLO film. The LLO layer is shown to be effective in suppressing the reverse and forward leakage current in the MIS diode. In particular, the MIS diode forward current is reduced by 7 orders of magnitude at a forward bias of 1 V compared to a conventional Ni-Au/III-nitride Schottky diode. [ABSTRACT FROM AUTHOR]

The gate-induced-drain-leakage of MOSFETs is analyzed to better understand the sub-threshold swing degradation of SiGe tunnel field-effect transistors and their band-to-band tunneling mechanism. The numerical model of the analysis is elaborated. Equivalent trap energy levels are extracted for Si and strained SiGe. It is found that the equivalent trap energy level in SiGe is shallower than that in Si. [ABSTRACT FROM AUTHOR]