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The role of threading dislocations in the intrinsic degradation of lateral GaN devices during high reverse bias stress tests (RBSTs) is largely unknown. We now present the results on lateral p-GaN/AlGaN/2DEG heterojunctions with a width of 200 μm in GaN-on-Si. A time-dependent permanent degradation of the heterojunction under high reverse bias and elevated temperatures can be observed, ultimately leading to a hard breakdown and device destruction. By using an integrated series p-GaN resistor, the device is protected from destruction and, consequently, the influence of dislocations on the degradation mechanism could be studied. Localization by emission microscopy could show that the transient current increase during a RBST is the result of the creation of a limited amount of highly localized leakage paths along the whole device width. We could establish a 1:1 correlation of leakage sites with a structural material degradation within the AlGaN barrier for nine individual positions on two different devices by planar transmission electron microscopy analysis. To unambiguously show whether dislocations in GaN-on-Si even should be considered a potential trigger for the RBST degradation in lateral heterojunctions, a combined planar and cross-sectional lamella approach was used for the first time for larger devices. This enabled the visualization of the three-dimensional propagation path of the dislocations close to the degradation sites. It was found that there is no statistically significant link between the material degradation and pre-existing dislocations. Our findings offer new insights into the GaN-on-Si material system, upon which upcoming power technologies are built upon. [ABSTRACT FROM AUTHOR]

Carbon impurities in GaN form both acceptors and donors. Donor-to-acceptor ratios (DARs) determine the semi-insulating behavior of carbon-doped GaN (GaN:C) layers and are still debated. Two models are discussed; both can theoretically achieve semi-insulating behavior: the dominant acceptor model (DAM, DAR < 1) and the auto-compensation model (ACM, DAR = 1). We perform a capacitance–voltage analysis on metal/GaN:C/nGaN (n-doped GaN) structures, exhibiting Fermi-level pinning in GaN:C, 0.7 eV above the valence band maximum. This observation coupled with further interpretation clearly supports the DAM and contradicts the ACM. Furthermore, we reveal a finite depletion width of a transition region in GaN:C next to nGaN, where carbon acceptors drop below the Fermi level becoming fully ionized. Calculation of the potential drop in this region exhibits DAR values of 0.5–0.67 for GaN:C with total carbon concentrations of 10 18 cm − 3 and 10 19 cm − 3 . Based on those results, we re-evaluate formerly published density functional theory (DFT)-calculated formation energies of point defects in GaN. Unexpectedly, growth in thermodynamic equilibrium with the bulk carbon phase contradicts our experimental analysis. Therefore, we propose the consideration of extreme carbon-rich growth conditions. As bulk carbon and carbon cluster formation are not reported to date, we consider a metastable GaN:C solid solution with the competing carbon bulk phase being kinetically hindered. DFT and experimental results agree, confirming the role of carbon at nitrogen sites as dominant acceptors. Under N-rich conditions, carbon at gallium sites is the dominant donor, whereas additional nitrogen vacancies are generated under Ga-rich conditions. [ABSTRACT FROM AUTHOR]

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We provide theoretical and simulation analysis of the small signal response of SiO2/AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, Cp, and conductance, Gp, . Cp, -voltage and Gp, -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance Rbr, and the effective channel resistance. In particular, in the spill-over region, the drop of Cp, with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of Rbr, with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density of interface traps, Dit, from the Gp,/ω vs. angular frequency ω curves. A peak in Gp/ω vs. ω occurs even without traps, merely due to the intrinsic frequency response of gate stack. Moreover, the amplitude of the Gp/ vs. ω peak saturates at high Dit, which can lead to underestimation of Dit. Understanding the complex interplay between the intrinsic gate stack response and the effect of interface traps is relevant for the development of normally on and normally off MIS high electron mobility transistors with stable threshold voltage. [ABSTRACT FROM AUTHOR]

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias <38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by ∼70%, are found after the off-state ∼50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability. [ABSTRACT FROM AUTHOR]

GaN-on-Si is a lateral technology and as such it allows the integration of high voltage High Electron Mobility Transistors and low voltage devices on the same chip, thus enabling the miniaturization and reduction of parasitic inductances. Due to the fact that integrated devices share a common substrate, the performance of one device can be significantly affected by the operation of another. The choice of the substrate bias is particularly important in the integrated half-bridge, a popular topology which includes a low- and a high-side device. A grounded substrate will cause vertical stress on the high-side device, while a floating substrate will couple with the high voltage, resulting in stress on the low-side device. This is highly problematic as the devices may fail to turn on or have a significantly increased RON. In this work, we carefully investigate the substrate coupling of a high-side and low-side device via backgating measurements. We demonstrate that the unwanted RON increase in the high side device could be suppressed by hole injection from the gate, if the gate is formed of a p-type material. [ABSTRACT FROM AUTHOR]

Exchange of carriers between the GaN channel and the dielectric/AlGaN interface in AlGaN/GaN metal insulator semiconductor high electron mobility transistors was recently attributed to a serial process of electron transport through the AlGaN barrier and electron trapping/emission at the interface. In this paper, the time constant related to barrier transport is evaluated from the measurements of time onset of threshold voltage drift in stress-recovery experiments. Temperature and forward gate bias dependent studies reveal an activation energy of 0.65 eV for the electron transport at zero bias being consistent with the estimated potential barrier of 0.75 eV at the dielectric/AlGaN interface. Thermo-ionic emission and defect assisted tunneling to near interface states are considered as transport mechanisms. [ABSTRACT FROM AUTHOR]

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulatorsemiconductor structures causes tremendous threshold voltage drifts, DVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, DNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of DNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation. [ABSTRACT FROM AUTHOR]

In this letter we present a quantum well infrared photodetector (QWIP), which is fabricated as a photonic crystal slab (PCS). With the PCS it is possible to enhance the absorption efficiency by increasing photon lifetime in the detector active region. To understand the optical properties of the device we simulate the PCS photonic band structure, which differs significantly from a real two-dimensional photonic crystal. By fabricating a PCS-QWIP with 100x less quantum well doping, compared to a standard QWIP, we are able to see strong absorption enhancement and sharp resonance peaks up to temperatures of 170 K. [ABSTRACT FROM AUTHOR]

We report on an annealing-induced “gate sinking” effect in a 2-nm-thin In0.17Al0.83N/AlN barrier high electron mobility transistor with Ir gate. Investigations by transmission electron microscopy linked the effect to an oxygen containing interlayer between the gate metal and the InAlN layer and revealed diffusion of oxygen into iridium during annealing. Below 700 °C the diffusion is inhomogeneous and seems to occur along grain boundaries, which is consistent with the capacitance-voltage analysis. Annealing at 700 °C increased the gate capacitance over a factor 2, shifted the threshold voltage from +0.3 to +1 V and increased the transconductance from 400 to 640 mS/mm. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is supplied to grow ZrO2 high-k gate dielectrics and fabricate InAlN/GaN metal oxide semiconductor (MOS) high electron mobility transistors (HEMTs). Ex situ chemical surface cleaning and optimised in situ InAlN surface pre-treatment by ALD lead to a substantial suppression of drain–source current collapse owing to a high-quality InAlN/oxide interface. In addition, the gate leakage current was suppressed by about three orders of magnitude. [ABSTRACT FROM AUTHOR]