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As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step. [ABSTRACT FROM AUTHOR]

With the consideration of higher modes, an attempt is made to develop a spectral-acceleration-based linear combination-type earthquake intensity measure (IM) for high-rise buildings. The modal mass participation factors are determined to take weighting coefficients. A parametric analysis on the correlation between IM and the maximum interstory drift that utilizes the bend-shear coupled continuum model yields a bilinear relationship between the optimal number of modes involved and structural fundamental period. The proposed IM and several other combination-type IMs are shown to be efficient and sufficient, while the scaling robustness of the proposed IM is more stable compared with that of fundamental-mode-based IMs. [ABSTRACT FROM AUTHOR]

A novel time‐interleaving analog adder used in externally compensated AMOLED/Micro‐LED systems is proposed. With a specialized pipeline architecture, the analog adder achieves lower power consumption and higher precision of digital‐to‐analog conversion. The maximum output error of the analog adder is only 3 mV while the nonlinear error is 0.0735%. [ABSTRACT FROM AUTHOR]

This paper presents a high-voltage analog adder with only four high-voltage transistors for source driver of AMOLED displays. It has high drive speed and voltage accuracy, and provides enhanced capacitance drive capability under a small quiescent current by exploiting two current comparators incorporated into differential amplification stage of class-B amplifier. [ABSTRACT FROM AUTHOR]

In this Letter, a low‐power, high‐speed output buffer for ultra‐large infrared focal plane arrays (IRFPAs) is proposed. This buffer adopts a shared trans‐impedance amplifier structure, which reduces parasitic resistance and capacitance of column‐level bus. A 1280 × 1024 array readout integrated circuit with 20 MHz output frequency is designed for cooled infrared detector using this novel structure. The chip has been realised with 0.35 μm 1P4M CMOS process and power consumption of the proposed single output buffer is 3.83 mW. Though the presented circuit has been designed for this design, it shows great potential to be employed in most ultra‐large readout integrated circuits. [ABSTRACT FROM AUTHOR]

A low‐power, high‐linearity, high‐charge handling capability two‐stage ADC‐based 384 × 288 size digital readout integrated circuits (ROIC) for infrared focal plane arrays are presented. A novel high‐speed, low‐power‐consumption comparator structure is proposed in this work. Moreover, the two‐stage ADC combines the pulse frequency modulation (PFM)‐based pixel‐level ADC and fine quantify module, improving the charge handling capability and the linearity of the readout circuit. The ROIC with 25 μm pixel pitch has been realised in 0.18 μm 1P6M CMOS process. The power consumption of the two‐stage ADC is 50 μW. The charge handling capability of the pixel is 2.3 Ge− and the non‐linearity of the proposed circuit is 0.09%. [ABSTRACT FROM AUTHOR]

A current-biased voltage-programmed (CBVP) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays is proposed. The pixel circuit can not only ensure an accurate and fast compensation for the threshold voltage variation and degeneration of the driving TFT and the OLED, but also provide the OLED with a negative bias during the programming period. The negative bias prevents the OLED from a possible light emitting during the programming period and potentially suppresses the degradation of the OLED. [ABSTRACT FROM PUBLISHER]

A low‐power time‐to‐digital converter (TDC) scheme for column‐level single‐slope analogue‐to‐digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3‐bit fine gray counter, which makes use of multi‐phase clocks from a delay‐lock‐loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two‐step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse‐fine inconsistency problem with a simulated ±0.1 least‐significant‐bit differential non‐linearity performance. [ABSTRACT FROM AUTHOR]

In this paper, a micromachined gyroscope system composed of a vibratory gyroscope with its interface ASIC is presented. The system adopts a DC sensing method to detect the capacitive motion, which is insensitive to the mismatch of the gyroscope capacitors and can eliminate high frequency signals from the chip. Therefore it offers a commendable noise performance with simplified topology. Low noise design can be achieved by a continuous-time charge sensitive amplifier with the input-referred noise voltage of 9.833 nV/rtHz at 10 kHz. A novel high voltage (HV) buffer is adopted in the drive mode to strengthen its drive signal, so that the common-mode voltage of it is made at 5 V that is compatible with the gyroscope. The HV buffer utilizes two sets of power supply to achieve both good noise performance and HV output. The ASIC chip is fabricated in the 0.35 μm 2P4M BCD HV process, and is 2.5×2.0 mm in dimension. The test results prove that the system achieves a stable closed-loop oscillation in the drive mode. Furthermore, the in-phase demodulation result of the gyroscope system achieves a nonlinearity of 0.14% within the sense range of 0°-500°/s. [ABSTRACT FROM AUTHOR]

This paper presents mathematical formulae showing that the distance mismatch for an uncentered proof mass in an accelerator sensor does not influence the linearity of the closed-loop accelerometer as a whole. This asymmetry in sensors only introduces an output voltage offset in the readout integrated circuit. Numerical simulation using Matlab/Simulink confirms the mathematical conclusion. The linear response after compensation with a conventional capacitor array is also simulated and analyzed. Results show that there is a loss in linearity. Similar results hold not only for the continuous-time architecture, but also for a time-divided architecture. A readout integrated circuit with a time-divided architecture is designed and fabricated using a 0.35 μm HV CMOS process. An accelerometer composed of a microelectromechanical system sensor with severe built-in distance mismatch and the designed readout integrated circuit is tested. Test results show that the nonlinearity of such accelerometer is within 0.3%. [ABSTRACT FROM AUTHOR]

A column‐level two‐step analogue‐to‐digital converter (ADC) structure for infrared focal‐plane array (IRFPA) is proposed. The first step adopts a 16‐column‐shared 6‐bit flash ADC to accomplish the coarse conversion of 16 columns one by one. Owing to the staggered code and correction, a dynamic comparator is adopted in the flash ADC and the power dissipation of a flash ADC averaged to one column in period is only 0.386 μW. The second step is SAR conversion of which the cycle time is prolonged. The input voltage variation of the comparator in the charge redistribution structure is decreased to tens of millivolts; so a 1.8 V power supply is adequate in spite of 5 V VFS. The power dissipation of this comparator is reduced to 5.966 μW. Also, the lower clock frequency of the SAR logic reduces the dynamic power. A 14‐bit two‐step ADC is designed in 0.18 μm process and the equivalent power dissipation of the proposed ADC structure for one column is <20 μW. [ABSTRACT FROM AUTHOR]

A low‐noise analogue frontend readout circuit is presented for VOx microbolometer infrared imager without thermo‐electrical cooler. A modified differential mirror structure with substrate temperature and self‐heating effect compensation ability is used, targeting below 40 mK noise equivalent temperature difference (NETD) with 17 μm pixel pitch. Noise characteristics are investigated to give an optimal trade‐off approach to reach lower NETD at same power consumption compared with traditional readout structures. [ABSTRACT FROM AUTHOR]