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Your search keyword '"Hyun Chul Sagong"' showing total 11 results
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11 results on '"Hyun Chul Sagong"'

8. A New Physical 1/f Noise Model for Double-Stack High-k Gate-Dielectric MOSFETs.

Author

Seung Hyun Song, Hyun-Sik Choi, Rock-Hyun Baek, Gil-Bok Choi, Mm-Sang Park, Kyung Taek Lee, Hyun Chul Sagong, Sang-Hyun Lee, Sung Woo Jung, Chang Yong Kang, and Yoon-Ha Jeong

Subjects
METAL oxide semiconductor field-effect transistors, DIELECTRICS, NOISE generators (Electronics), ELECTRIC fields, QUANTUM tunneling
Abstract

In this letter, a new physical 1/f noise model is developed for double-stack high-k dielectric MOSFETs. This new model modifies the trapping-time-constant term in multistack unified noise model. Conventional 1/f noise model is built on the simple square potential approximation which did not account the electric field dependence on trapping time constant. The new model takes into account of a resultant tunneling process from the actual sloped potential in order to eliminate the discrepancies of dielectric trap density on the dielectric thickness and the gate bias. Our model successfully predicts 1/f noise data obtained from SiO2/HfO2 double-stack high-k devices with various gate-dielectric thicknesses using a single set of modeling parameter. [ABSTRACT FROM AUTHOR]

Published
2009
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9. Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation.

Author

Chang-Woo Sohn, Chang Yong Kang, Rock-Hyun Baek, Do-Young Choi, Hyun Chul Sagong, Eui-Young Jeong, Jeong-Soo Lee, Kirsch, Paul, Jammy, Raj, Lee, Jack C., and Yoon-Ha Jeong

Abstract

We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-Hfin ratio significantly reduces Cpara/W, which renders DG FinFETs comparable to planar FETs. Process variation on Wfin and Hfin should be controlled, otherwise, the Cpara uniformity will be worse for DG FinFETs than it is planar FETs. [ABSTRACT FROM PUBLISHER]

Published
2012
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