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This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 mm². The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-½ DVB-T mode is -98 dBm at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated Σ-Δ fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1° integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands. [ABSTRACT FROM AUTHOR]

Digital video reception is emerging as the latest feature toward multimedia-enriched handheld devices. Mobile battery-operated devices require small-size tuners that consume low power and are amenable to single-chip integration with the baseband demodulator. Following an overview of the system and circuit-level implementation challenges of mobile TV standards such as DVB-H and T-DMB, this article presents a dual-band direct conversion tuner for DVB-H. Architecture and circuit trade-offs are discussed, and detailed measurements are presented. The tuner occupies 9.7 mm² and achieves a 4 dB NF at both UHF and L-band, eliminating the need for an external LNA. By using a fractional-N synthesizer both 470-890 MHz and 1.4-1.8 GHz bands are supported, while achieving an integrated phase noise of less than -41 dBc. Sixth-order low-pass filters support channel bandwidths from 4 to 10 MHz. [ABSTRACT FROM AUTHOR]

A data acquisition system for processing signals produced by direct photon conversion sensors, primarily for applications in digital X-ray imaging, has been developed. The system comprises a custom-made PCI card, a front-end readout ASIC, and a digital counting ASIC. The operation of the readout ASIC is optimized for input capacitance of 2 pF per strip, which includes both the detector and the interconnection capacitance. The dynamic range of the system is extended from 30 up to 250 keV. Since the readout chip also includes a polarity select circuit, the system is suitable for applications with electron or hole collecting detectors. Due to the adopted readout architecture the counting rate achieved is extremely high, up to 3 MHz, while the measured noise was around 1200 electrons for 2 pF detector capacitance. The real-time imaging system is under evaluation in combination with CdTe detectors as front-end of a luggage inspection system. In this paper, the architecture and the performance of the two ASICs of the system are presented. [ABSTRACT FROM AUTHOR]

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-µm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm². [ABSTRACT FROM AUTHOR]

A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 μm CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is $$270\mu {\text{m}} \times {\text{150}}\mu {\text{m}}$$ . The gain at the shaper output is 378 mv/fC, theENC is 16 $$e^ - $$ rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is $$13\;e^ - $$ rms with 240 nsec peaking timeand 1.4 μsec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF. [ABSTRACT FROM AUTHOR]

Focuses on the design characteristics of an ultra fast current amplifier with a novel active feedback loop. Creation of a prototype; Nanoseconds to which the baseline of the electronic circuit recovers; Typical applications of amplifier.