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During Cu/low-kdamascene integration, plasma ash can introduce a thin modified layer on the trench sidewall of low-kdielectrics. This plasma ash modified layer can influence the time-dependent dielectric breakdown (TDDB) lifetime distribution. In this paper, we investigated the plasma ash modified layer effect on the TDDB thermal activation energy of a CVD SiOC:H low-kdielectric (k= 3) integrated in Cu damascene structures. We found that for the 'non-modified' SiOC:H low-kdielectric combined with sealing metal diffusion barriers, the TDDB thermal activation energy is close to zero. With the introduction of a plasma ash modified layer, the apparent TDDB thermal activation energy increases. By means of thermal desorption spectroscopy on blanket films and energy-filtered TEM analysis on patterned structures, the increase of TDDB thermal activation energy is correlated with plasma ash induced moisture uptake in the CVD SiOC:H low-kdielectric. [ABSTRACT FROM AUTHOR]

In this work, we present the impact of S/D contact formation, that is, by SiN plasma doping (hydrogen incorporation), metallic reduction (by calcium) and by argon plasma (compositional change) on NBIS instabilities of self-aligned a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

We validate a model which is a combination of multiple trapping and release and percolation model for describing the conduction mechanism in amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT). We show that using just multiple trapping and release or percolation model is insufficient to explain TFT behavior as a function of temperature. We also show the intrinsic mobility is dependent on temperature due to scattering by ionic impurities or lattice. In solving the Poisson equation to find the surface potential and back potential as a function of gate voltage, we explicitly allow for the back surface to be floating, as is the case for a-IGZO transistors. The parameters for gap states, percolation barriers and intrinsic mobility at room temperature that we extract with this comprehensive model are in good agreement with those extracted in literature with partially-complete models. [ABSTRACT FROM AUTHOR]

In this work, we perform an in-depth analysis of electron-trapping in AlGaN/GaN Schottky barrier diodes under constant voltage (VAC = −100 V) off-state stress conditions. The current–voltage (I–V) characteristics of the diode after stressing show a leakage reduction and on-state degradation due to electron-trapping occurring in the vicinity of the Schottky contact. Capacitance–voltage (C–V) measurements confirm an increase of the barrier height and the on-resistance of the stressed device. Furthermore, the on-resistance increase has been studied with different temperatures and stressing times. By TCAD simulations, a lateral extension of the “trapped region” at the AlGaN/Si3N4 interface has been visualized and can qualitatively explain the phenomenon of higher on-resistance increase at higher temperatures. [ABSTRACT FROM AUTHOR]

We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation. [ABSTRACT FROM AUTHOR]

This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge-source for nTFET, In0.6Ga0.4As-source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%-75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNT) are known to be materials with potential for manufacturing sub-20 nm high aspect ratio vertical interconnects in future microchips. In order to be successful with respect to contending against established tungsten or copper based interconnects, though, CNT must fulfil their promise of also providing low electrical resistance in integrated structures using scalable integration processes fully compatible with silicon technology. Hence, carefully engineered growth and integration solutions are required before we can fully exploit their potentialities. This work tackles the problem of optimizing a CNT integration process from the electrical perspective. The technique of measuring the CNT resistance as a function of the CNT length is here extended to CNT integrated in vertical contacts. This allows extracting the linear resistivity and the contact resistance of the CNT, two parameters to our knowledge never reported separately for vertical CNT contacts and which are of utmost importance, as they respectively measure the quality of the CNT and that of their metal contacts. The technique proposed allows electrically distinguishing the impact of each processing step individually on the CNT resistivity and the CNT contact resistance. Hence it constitutes a powerful technique for optimizing the process and developing CNT contacts of superior quality. This can be of relevant technological importance not only for interconnects but also for all those applications that rely on the electrical properties of CNT grown with a catalytic chemical vapor deposition method at low temperature. [ABSTRACT FROM AUTHOR]