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We report low-energy proton and low-energy alpha particle SEE data on a 32 nm SOI CMOS SRAM that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 MeV. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment. [ABSTRACT FROM PUBLISHER]

The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps. [ABSTRACT FROM PUBLISHER]

We apply a model and heavy-ion cross section data to predict the potential that one single event upset (SEU) will induce multiple bit errors (MBEs) by the next clock-cycle of a synchronous design. [ABSTRACT FROM PUBLISHER]

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts. [ABSTRACT FROM PUBLISHER]

A 1 GeV/amu ^56Fe ion beam allows for true 90^\circ tilt irradiations of various microelectronic components and reveals relevant upset trends at the GCR flux energy peak. Three SRAMs and an SRAM-based FPGA evaluated at the NASA Space Radiation Effects Laboratory demonstrate that a 90^\circ tilt irradiation yields a unique device response. These tilt angle effects need to be screened for, and if found, pursued with radiation transport simulations to quantify their impact on event rate calculations. [ABSTRACT FROM PUBLISHER]

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss. [ABSTRACT FROM AUTHOR]

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events. [ABSTRACT FROM AUTHOR]

We report on complementary use of two-photon absorption laser and heavy-ion SEE testing to evaluate the single-event response of SDRAMs. The tandem testing technique helps disentangle the response of devices exhibiting multiple SEE modes. [ABSTRACT FROM AUTHOR]

A methodology for evaluating various types of FPGAs targeted for space missions is presented. The premise is to supply unambiguous SEE information so that flight-projects may insert the optimal device for their application. [ABSTRACT FROM AUTHOR]

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed. [ABSTRACT FROM PUBLISHER]