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Abstract: We present a method to obtain Si-fins with a critical dimension (CD) below 20nm, separated by a minimum distance of 25nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350nm pitch resist pattern defined by 193nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200mm wafer. The average CD is 17nm in the center of the wafer and 18nm at the edge. The LWR is 3nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H2 anneal) further reduce the CD to 13nm. [Copyright &y& Elsevier]

Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies available in 3-D-Stacked IC devices do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3-D System on Chip integration technology schemes enable the increase of 3-D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases that were applied in this pathfinding and development phase are demonstrated. Techniques, such as wafer level interferometry, wafer edge inspection and metrology, wafer front side metrospection, and wafer high resolution topography techniques were used to investigate process issues. Metrology data enabled us to determine where the extreme wafer thinning process could be improved. The same techniques were used to validate the improvements and to monitor process stability. [ABSTRACT FROM AUTHOR]

The article reports on the pathfinding and development of the extreme semiconductor wafer thinning process by using the in-line metrology methods. It examines where the extreme wafer thinning process can be improved. It is said that different thinning techniques like grinding, polishing and etching were evaluated during the extreme wafer thinning process pathfinding and development.

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

Abstract: FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22nm node 6T-SRAM cell. Key in this work was achieving the required CD and profile target specs for the fin and the gate level. Also, the implant levels, though still a 450nm pitch, turned out to be more difficult than expected because of the underlying topography. All this work resulted in the first electrically functional 22nm node SRAM cell, with the contact and metal level exposed on the ASML EUV α-demo tool. [Copyright &y& Elsevier]

Abstract: The integration of air gaps for advanced Cu interconnects is mandatory to achieve the performances required for high performance integrated circuits (ICs). The interest of their introduction as a function of the chosen architecture, i.e. hybrid (i.e. air cavities at metal levels with a low-K material at via level) or full homogenous air gaps with an effective relative constant close to 1, is discussed in terms of signal propagation requirements for delay, crosstalk and delay increased by crosstalk. The different approaches currently investigated within the microelectronic community are classified into two main categories depending on the use of a non-conformal plasma enhanced chemical vapor deposition (PE-CVD) including innovative alternatives or the removal of a sacrificial material during a specific technological operation. While the first technique,, faces many integration issues that can be alleviated at the detriment of the global performances, the second approach may be all the more promising as well-known materials such as USG or SiOC are now introduced as sacrificial dielectrics as an alternative to degradable polymers. However, it is evidenced from published results that air gaps integration maturity permits their introduction for the 32nm technology node high performance ICs. [Copyright &y& Elsevier]