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Content Addressable Memory (CAM) is a special memory used in search engines for numerous applications, especially in network routers for packet forwarding. The CAM operation begins with pre-charging followed by evaluating the match-lines (MLs) for searching the data in the stored memory. CAM stores unique words in their array of cells such that only one word is matched for a given search word. ML associated with matched word retains its state and the remaining MLs drain their charge. Ternary content addressable memory (TCAM) is a fast lookup hardware device used for high-speed packet forwarding. However, significant power consumption and high cost limits its versatility and popularity. In this paper, a design has been made for TCAM architecture with pre-charge controller. The pre-charge controller helps in predicting the mismatched MLs during pre-charge phase. This prediction happens at an early stage and helps in terminating the pre-charging of the line. This assures the design of TCAM which consumes low power and also improves the performance. The proposed early predict 8 x 8 TCAM architecture simulations were performed in 45nm technology node using Cadence Virtuoso. The proposed TCAM design exhibits 16.6% reduction in power, 24.7% decrement in delay and 37.1% minimization in energy metric than basic TCAM NOR. [ABSTRACT FROM AUTHOR]

Dynamic Read Destructive Fault (dRDF) is the outcome of resistive open defects in the core cells of static random-access memories (SRAMs). The sensitisation of dRDF involves either performing multiple read operations or creation of number of read equivalent stress (RES), on the core cell under test. Though the creation of RES is preferred over the performing multiple read operation on the core cell, cell dissipates more power during RES than during the read or write operation. This paper focuses on the reduction in power dissipation by optimisation of number of RESs, which are required to sensitise the dRDF during test mode of operation of SRAM. The novel pre-charge architecture has been proposed in order to reduce the power dissipation by limiting the number of RESs to an optimised number of two. The proposed low power architecture is simulated and analysed which shows reduction in power dissipation by reducing the number of RESs up to 18.18%. [ABSTRACT FROM AUTHOR]

To make a Lithium Ion Battery (LIB) reliably rechargeable over many cycles, its graphite-based negative electrode requires the solid electrolyte interphase (SEI) as a protection layer. The SEI is formed through chemical and particularly electrochemical side reactions of electrolyte components in the first charging cycle(s) after manufacturing of a LIB. The SEI ideally serves two purposes: (i) act as a sieve permeable to Li ions but not to other electrolyte components and (ii) passivate the electrode against further electrolyte decomposition. Core element of conventional SEI formation is a lengthy, low-current galvanostatic charging step, which due to its time consumption contributes heavily to cell manufacturing costs. Here, we report on some non-conventional SEI formation protocols for composite carbon electrodes, inspired by recent experimental findings at smooth model electrodes. Acknowledging that the SEI forms in two main steps, taking place in a high-potential and a low-potential region, respectively, we demonstrate that less time spent in the high-potential region not only makes the process faster but even yields SEIs with superior kinetic properties. We tentatively explain this via basic rules of thin film growth and the role of grain boundaries for ion transport. We also report on the positive influence of multi-frequency potential modulations applied between high-potential and low-potential formation. Given that any new cell chemistry in principle requires its own tailor-made formation process, technologic success of future LIB cells will benefit from a systematic, well-understood toolbox of formation protocols. This paper is meant as a first step, highlighting potentially low-hanging fruits, but also flagging the demand for further systematic studies on model systems and on commercially manufactured cells. [ABSTRACT FROM AUTHOR]

• In this paper, the circuit that can perform store and restore operation of nvSRAM is designed. The suggested auto store circuit is consisted by two small circuit parts (store circuit and restore circuit). • The nvSRAM replaced its access transistors to flash memory needs higher voltage for store operation. It demands much energy and additional voltage source to store a data. • Besides restore process is also needed when it recalls the data to SRAM part. The suggested store and restore circuit charges their capacitors when power is supplied. When the power is off, the store circuit discharges its capacitors and applies higher voltage to word line for the store operation. • And when the power is supplied again, the restore circuit discharges its capacitor and applies pre-charge voltage and restore voltage to bit line and word line for the restore operation. • The Auto store circuit does not need additional voltage source because it shares source with nvSRAM and can perform the store, restore operation in sudden power off. In this paper, an auto-store circuit that can perform a store and restore operation of non-volatile SRAM (nvSRAM) with access transistor whose gate stack is Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is designed. The suggested auto-store circuit is consisted by two small circuit parts of a store and restore circuit. The store circuit moves data in SRAM cell into SONOS device before power turns off while a restore circuit recalls the data to SRAM cell when the power is resupplied. When the nvSRAM replaces its conventional access transistor with the SONOS flash memory device, higher word line voltage is needed for a store operation. It demands much energy and additional voltage source to store a data. To overcome this disadvantage, the capacitor component is added in the store and restore circuit which is charged during the normal operation mode. At the moment of the power-off, the store circuit discharges the capacitors and applies higher voltage to the word line for the store operation. When the power is supplied again, the restore circuit discharges the capacitor and applies pre-charge voltage and restore the data to the bit line and word line. The simulation results show that the suggested auto store circuit can perform the store, restore operation in the sudden power off without an additional voltage source. [ABSTRACT FROM AUTHOR]

A new memory design with a simple six-transistor memory cell achieves an enhanced read static noise margin. Based on using 'pre-equalize' rather than 'pre-charge' at the beginning of a read operation, the cross-coupled inverters of the memory cell have a switching threshold close to that of the conventional CMOS inverter circuit, thus achieving both compactness and increased data stability. The proposed can also potentially dramatically decrease power dissipation in conventional memory counterparts. Both simulations and measurements were carried out as proof of concept. The proposed memory hardware techniques are simple to implement and highly practical, making it quite competitive with other currently used methods. [ABSTRACT FROM AUTHOR]