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Resistive switching memory (RRAM) based on the redox-induced conductivity change in some metal oxides attracts considerable interest as a new technology for next-generation nonvolatile electronic storage. Although resistance-switching phenomena in several transition metal oxides have been known from decades, the details of the switching mechanisms and the nature of the different resistive states are still largely debated. For nonvolatile memory applications, the scaling potential of RRAMs is the most relevant issue, and understanding the scaling capability of RRAM devices requires a sound interpretation of resistance-switching operation and reliability aspects. This work addresses the scaling dependence of RRAM switching parameters. The dependence on the electrode area and on the size of the conductive filament (CF) responsible for low-resistance memory state is investigated. The RRAM conduction modes depending on CF size are discussed based on temperature dependent resistance analysis. Reset characteristics in different resistance states are explained by a Joule heating model for CF oxidation. [ABSTRACT FROM AUTHOR]

Nanowires (NWs) represent a logical pathway to extreme scaling of semiconductor devices in the single-digit nanometer scale. Combined with the inherent scalability of the resistive switching memory (RRAM), where the switching region consists of a conductive filament as small as a single atom, NWs may provide an ideal approach to reduce the device area to a range not accessible to conventional lithography. This work reviews NW-based RRAM (NWRRAM) devices. The different approaches to NWRRAMs, including (i) switching in a single metal-oxide NW, (ii) switching in a heterostructured NW with a metal-oxide segment sandwiched between NW metallic electrodes and (iii) switching in a core-shell NW, are discussed. The latter approach is then presented in detail, covering the assembly issues, the robust switching and reliability characteristics, and the scaling outlook. [ABSTRACT FROM AUTHOR]

Abstract: Resistive-switching memory (RRAM) is receiving a growing deal of research interest as a possible solution for high-density, 3D nonvolatile memory technology. One of the main obstacle toward size reduction of the memory cell and its scaling is the typically large current I reset needed for the reset operation. In fact, a large I reset negatively impacts the scaling possibilities of the select diode in a cross-bar array structure. Reducing I reset is therefore mandatory for the development of high-density RRAM arrays. This work addresses the reduction of I reset in NiO-based RRAM by control of the filament size in 1 transistor–1 resistor (1T1R) cell devices. I reset is demonstrated to be scalable and controllable below 10μA. The significance of these results for the future scaling of diode-selected cross-bar arrays is finally discussed. [Copyright &y& Elsevier]

Abstract: Data retention in phase-change memory (PCM) devices is the result of two physical phenomena: structural relaxation (SR) and crystallization of the amorphous chalcogenide material. Although the two processes are rather different, we show in this paper that a common physical interpretation for SR and crystallization kinetics is possible. Activation energies and Arrhenius pre-factors for SR and crystallization are found to coherently obey a Meyer–Neldel rule and are explained by many-body thermal excitation of weakly-bonded and normally-bonded clusters, respectively. [Copyright &y& Elsevier]

Abstract: Phase change memory (PCM) is the most performing non-volatile memory-technology alternative to FLASH. In order to design optimized cells, in term of geometry and materials, for present and future technological nodes, physics-based models for readout, programming and data retention are required. In this work, transport and phase-change modeling in PCM cell is reviewed and used to discuss (1) the programming-current reduction through geometry optimization, (2) the trade-off between programming current and readout resistance and (3) the program disturb phenomenon. In particular, scaling of PCM is extensively investigated, comparing the impact of isotropic and non-isotropic scaling on cell programming-current and program-disturb. Recent developments and open issues in PCM physical modeling are finally presented. [Copyright &y& Elsevier]

Abstract: In order to validate phase change memory (PCM) technology, the programming reliability, in terms of reading window between the programmed and erased state, must be guaranteed at array level with an error less then 1 part-per-billion. The reset distribution is significantly influenced by the quenching operation [Mantegazza D, Ielmini D, Pirovano A, Gleixner B, Lacaita A L, Varesi E, et al. Electrical characterization of anomalous cells in phase change memory arrays. IEDM Tech Dig 2006:53–56]. In this paper this phenomenon is explained in terms of PCM active material crystallization statistics. A significant spread in the crystallization times among PCM cells is detected both in the write-reset operation from the melted-amorphous state (quenching) and in the erase-set operation from the solid-amorphous state. At statistical level, a correlation between set at high and low temperatures and quenching behavior of cells is found, allowing to describe the programming distributions uniquely in terms of crystallization times statistics. [Copyright &y& Elsevier]

Abstract: Emerging phase-change memory (PCM) technology for non-volatile applications presents many potential advantages in terms of scalability, endurance and program/read speed. While several integration issues have still to be solved before achieving volume-production stage, the fundamental physics of chalcogenide switching and phase-change behaviour has still to be comprehensively understood. This paper provides an in-depth analysis of the switching and programming transient in PCM cells. It is shown that the cell parasitic capacitance can lead to a marked current overshoot in the programming transient. As evidenced by experiments, this overshoot is able to melt and quench the active material as in a reset operation. The parasitic reset results in a series distribution of crystalline and amorphous phases after program. The analysis of array cell capacitance instead indicates that no parasitic reset is to be expected, allowing for a localized crystallization during program, as previously obtained by numerical simulations. [Copyright &y& Elsevier]

Abstract: Flash memories represent today a mainstream technology, finding ever increasing applications for both high-density data storage and embedded systems. However, as we step into the gigabit era, the Flash scalability is becoming increasingly difficult, and technological solutions to scale cell area and tunnel oxide thickness beyond the 45nm node are still unknown [1]. Among the major reliability concerns, the data loss through tunnel-oxide leakage in few tail cells after program/erase (P/E) cycling is expected to increase as the oxide thickness is downscaled and the projected number of P/E cycles is increased, according to the ITRS [2]. This may put severe limitations to thickness reduction and overall Flash scaling. To address this challenge, an adequate physical understanding of the problem is thus essential, allowing to a) draw physically-based estimation of failure probability and b) quantitatively assess the oxide defect density compatible with Flash scaling. The paper reviews the recent developments into these critical issues: with a focus on data retention, we discuss the characterization methodologies for reliability estimation, the physical and statistical models for predicting the reliability of next Flash generations and the scaling perspectives of the Flash technology. [Copyright &y& Elsevier]

Metal oxides can display resistance transition by the application of suitable electrical pulses, and this behavior is exploited for the development of resistive-switching memory devices. Here we report time-resolved electrical measurements demonstrating that the transition from the insulating to the metallic-conductivity state in NiO is first triggered by a threshold switching, i.e., an electronic transition to a highly conductive state typically observed in disordered semiconductors. Evidence for the possibility of subnanosecond transitions to low resistance is shown. Numerical simulations of threshold switching and Joule heating are finally presented, highlighting the role of the parasitic capacitance in the set transition. [ABSTRACT FROM AUTHOR]

The structural relaxation (SR) process in an amorphous chalcogenide material (Ge2Sb2Te5) is studied by electrical measurements on phase-change memory devices. SR induces a change in the conduction regime from Poole to Poole–Frenkel transport, evidencing a temperature accelerated defect-annihilation process. Based on an Arrhenius kinetics with distributed activation energies, a temperature-acceleration law is shown, relating the time to reach a specific relaxed state to the temperature during isothermal experiments. This law is demonstrated comparing the time evolution of resistance for different temperatures. These results allow for a significant time reduction in reliability testing of devices and materials affected by SR. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) has the potential of accelerating data-intensive computing tasks, such as inference and training of neural networks, by the matrix vector multiplication (MVM) in the crosspoint array. As the array size increases, however, a significant problem arises due to the parasitic IR drop at row and column lines. Understanding and compensating IR drop is essential to enable high-density accelerators of MVM. This work presents an analytical model for the IR drop and a numerical algorithm capable of accelerating the nodal analysis of crosspoint arrays up to five orders of magnitude with respect to SPICE analysis. The numerical algorithm is used to study the impact of array size, data density, device/wire resistance, and nonlinearity on the IR drop and the related loss of accuracy in IMC. We also derive two simple compensation schemes and an architectural solution for the mitigation of IR drop that are able to increase the accuracy of neural networks from 59% up to 96.6%, compared to an ideal accuracy of 97%. [ABSTRACT FROM AUTHOR]

A gradual uncontrollable increase in the resistivity of the amorphous phase of phase-change alloys, such as Ge2Sb2Te5, known as drift, is a serious technological issue for application of phase-change memory. While it has been proposed that drift is related to structural relaxation, no direct structural results have been reported so far. Here, we report the results of Ge L3-edge x-ray absorption measurements that suggest that the drift in electrical conductivity is associated with the gradual conversion of tetrahedrally coordinated Ge sites into pyramidal sites, while the system still remains in the amorphous phase. Based on electronic configuration arguments, we propose that during this process, which is governed by the existence of lone-pair electrons, the concentration of free carriers in the system decreases resulting in an increase in resistance despite the structural relaxation towards the crystalline phase. [ABSTRACT FROM AUTHOR]

Resistive switching in binary metal oxides consists of conductivity changes originating from the electrical creation/dissolution of conductive filaments (CFs) at nanoscale. The investigation of CF local properties can only be achieved through physical and electrical studies at the scale of 10 nm or less, that is, the characteristic size of CFs. This work reports on the direct manipulation of individual CFs formed through insulating NiO films by conductive atomic force microscopy (CAFM) and the comparison between forming/reset processes induced by CAFM and those observed in large-area devices with the same NiO film. The switching variability due to local defects, such as grain boundaries and dislocations, is directly evidenced by CAFM during electroforming process. Our results also indicate that the forming voltage under CAFM can be significantly smaller than the one observed in large-area devices, thus providing evidence for the electric-field enhancement underneath the CAFM tip. Filament deactivation, or reset, at extremely low currents close to 100 nA is demonstrated and described in terms of electrode-limited CF. These results suggest that device engineering and CF size limitation may allow for a significant reduction of forming voltage and reset current in resistive switching random-access memory switching. [ABSTRACT FROM AUTHOR]

The time-stability of the electrical characteristics of chalcogenide materials is one of the most important issues for their use in nonvolatile solid state memory applications. In particular the electrical conduction of the glassy phase evolves with time due to two different physical phenomena: the crystallization and the so-called low conductivity drift. Despite the physics of crystallization having been extensively studied in literature, the latter is mainly described by phenomenological relationships, and its physical comprehension is still under discussion. In this paper we study the amorphous phase low-field conductivity drift and its dependence on the temperature experienced by the device. We developed an experimental procedure able to separate the reversible change in the electrical conductivity with temperature due to the material semiconductorlike behavior from the nonreversible one related to the drift mechanism. A drift model explaining such nonreversible conductivity change as a band diagram modification is also provided and calibrated on experimental data. The present work finally introduces alternative metrics for drift quantification that can be useful in order to compare different materials. [ABSTRACT FROM AUTHOR]

Threshold voltage (VT) is an important parameter in phase change memory (PCM), marking the minimum voltage needed to program the memory device. In this work, we demonstrate that subthreshold pulses at V < VT can induce an increase of VT. The pulse-induced modification of VT is explained primarily due to the Joule heating during VT measurement accelerating the structural relaxation in the amorphous phase-change material. Our results demonstrate that VT can be adjusted through applied voltage pulses in the subthreshold regime, allowing the stabilization of programmed PCM states. [ABSTRACT FROM AUTHOR]

In a neural network, neuron computation is achieved through the summation of input signals fed by synaptic connections. The synaptic activity (weight) is dictated by the synchronous firing of neurons, inducing potentiation/depression of the synaptic connection. This learning function can be supported by the resistive switching memory (RRAM), which changes its resistance depending on the amplitude, the pulse width and the bias polarity of the applied signal. This work shows a new synapse circuit comprising a MOS transistor as a selector and a RRAM as a variable resistance, displaying spike-timing dependent plasticity (STDP) similar to the one originally experienced in biological neural networks. We demonstrate long-term potentiation and long-term depression by simulations with an analytical model of resistive switching. Finally, the experimental demonstration of the new STDP scheme is presented. [ABSTRACT FROM AUTHOR]

Abstract: Resistive switching memory (RRAM) devices are attracting an increasing interest as a possible future technology for ultra-scaled, high-density nonvolatile/dynamic memory. Although the RRAM concept is promising from the integration and scaling viewpoints, the switching mechanism and its controllability are still under debate. This paper addresses the modeling of reset and retention processes in unipolar resistive-switching memory devices. Reset transition and data loss are described in terms of the dissolution of a conductive filament, which is modeled by thermally-activated diffusion of defects/dopants. Carrier transport, Joule heating and diffusion of oxygen ions/vacancies during the electrical pulse and/or the annealing are modeled within a 3D numerical solver. The model can account for the observed dependence of reset voltage on the width of the applied triangular pulse and on the initial resistance for NiO-based RRAM devices. Retention simulations as a function of annealing temperature also agree with available data. The model provides a first example of device simulation tool for the design and the exploration of scaling and performance of RRAM cells. [Copyright &y& Elsevier]

Abstract: We present results of 3D Monte Carlo simulation of nanocrystal memory cells, investigating the impact of edge and percolation effects on the achievable threshold voltage window. While edge effects reduce the performance for narrow cells, percolation can play a beneficial role for W scaling, but is critical when scaling L. To reduce edge effects, a structure with non-overlapped trenches is proposed and investigated, showing that it can improve the performance by about 20% in terms of . [Copyright &y& Elsevier]

Aim of this work is the investigation of the impact of gate stack process on conduction and reliability of NMOSFET and PMOSFET in 0.18 μm dual-gate technology. Different poly-Si gate depositions and annealing oxidations have been compared, showing a strong impact on conduction characteristics only in PMOSFET in inversion mode. The differences have been ascribed to the contribution of electron tunneling through interface states at the poly-Si/SiO2 interface, whose density depends on the poly-Si grain dimension. STEM cross-sections have indeed shown completely different grain size depending on the gate stack technology. A significantly different reliability performance is found in correspondence. [Copyright &y& Elsevier]

In a phase change memory (PCM), the device resistance increases slowly with time after the formation of the amorphous phase, thus affecting the stability of stored data. This work investigates the resistance drift in thin films of amorphous Ge2Sb2Te5 and in PCMs, demonstrating a common kinetic of drift in stressed/unstressed films and in the nanometer-size active volume of a PCM with different stress levels developed via stressor layers. It is concluded that stress is not the root cause of PCM drift, which is instead attributed to intrinsic structural relaxation due to the disordered, metastable nature of the amorphous chalcogenide phase. [ABSTRACT FROM AUTHOR]