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The efficiency and cost of silicon physically unclonable function (PUF)-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses (PRs) under varying operational circumstances. Error-correcting codes (ECCs) can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying PUF is very noisy. When designing a PUF-based key generator, a more reliable PUF will result in a less complex ECC decoder and a smaller PUF footprint, and hence, an overall more efficient implementation. This paper proposes novel insight and resulting method for reducing noise on memory-based PRs, based on adapting supply voltage ramp-up time to ambient temperature. Circuit simulations on 45 nm low-power CMOS, as well as silicon measurements are presented to validate the proposed method. Our results demonstrate that choosing an appropriate voltage ramp-up for enrollment and adapting it according to the ambient temperature at key-reconstruction is a powerful method which makes memory-based PR noise up to 3 \times smaller. In addition, this paper investigates the competitiveness of integrating the proposed method in a commercial product; the investigation is done in two phases. First by determining the saved area, and second by implementing a circuit that maps the ambient temperature into an appropriate voltage ramp-up. The results show that the new system costs up to 82.1% less area while it delivers up to 3 \times higher reproducibility. [ABSTRACT FROM PUBLISHER]

Memristor-based memory technology, also referred to as resistive RAM (RRAM), is one of the emerging memory technologies potentially to replace conventional semiconductor memories such as SRAM, DRAM, and flash. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques, and reliability improvement. However, research on (manufacturing) test for yield and quality improvement is still in its infancy stage. This paper presents fault analysis and modeling for open defects based on electrical simulation, introduces fault models, and proposes test approaches for RRAMs. The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests. The paper also presents a new Design-for-Testability (DfT) concept to facilitate the detection of the unique faults. Two DfT schemes are developed by exploiting the access time duration and supply voltage level of the RRAM cells, and their simulation results show that the fault coverage can be increased with minor circuit modification. As the fault behavior may vary due to process variations, the DfT schemes are extended to be programmable to track the changes and further improve the fault/defect coverage. [ABSTRACT FROM AUTHOR]

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions. [ABSTRACT FROM AUTHOR]

One of the key challenges in 3D Stacked-ICs (3D-SIC) is to guarantee high product quality at minimal cost. Quality is mostly determined by the applied tests and cost trade-offs. Testing 3D-SICs is very challenging due to several additional test moments for the mid-bond stacks, i.e., partially created stacks. The key question that this paper answers is what is the best test flow to be used in order to optimize the overall cost while realizing the required quality? We first present a framework covering different test flows for 3D Die-to-Wafer (D2W) stacked ICs. Thereafter, we present a cost model that allows us to evaluate these test flows. The impact of different test flows on the overall 3D-SIC cost for several die yields and stack sizes are investigated; a breakdown of the cost into test, manufacturing and packaging cost is also provided. Our simulation results show that both the test cost and the overall cost in D2W stacking strongly depends on the selected test flow; test flows with pre-bond and mid-bond stacking tests (performed during the stacking process) show a higher test cost share, but significantly reduce the overall 3D-SIC cost. [ABSTRACT FROM AUTHOR]

With the continued advances in miniaturization, bit-line (BL) coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of BL coupling on the faulty behavior of defective dynamic RAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a Spice simulation model. Two BL coupling mechanisms are identified (pre-sense and post-sense coupling), which are found to have a partly opposing effect on the faulty behavior. It is shown that BL coupling causes a special kind of coupling fault between adjacent memory cells. In addition, the influence of BL twisting on the faulty behavior of the memory is analyzed and simulated. The results indicate strong correspondence between theory and simulation and show the importance of Spice simulation as a vital tool for fault analysis. [ABSTRACT FROM AUTHOR]

This paper presents a complete electrical analysis of Address decoder Delay Faults ‘ADFs’ caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests. [ABSTRACT FROM AUTHOR]

This paper improves upon the state of the art in the testing of intraword coupling faults (CFs) in word-oriented memories. It first presents a complete set of fault models for intraword CFs. Then, it establishes the data background sequence and tests for each intraword CF, as well as a test with complete fault coverage of the targeted faults. All introduced tests will be evaluated industrially, together with the most well-known memory tests. The tests will be applied to big arrays with an interleaved bit-organization as well as to small arrays with an adjacent bit-organization in order to investigate the influence of the memory organization on the intra-word CFs. The test results show that the intraword CFs are also significantly important for interleaved memories, even when the cells within a single cell are not physically adjacent. This is due to coupling between the adjacent bit lines and word lines running across the memory array. The paper concludes that Intraword CFs should be considered for any serious test purpose or leave substantial defects undetected, especially when considering a high-volume production and a very low defect-per-million (DPM) level. [ABSTRACT FROM AUTHOR]

The analysis of linked faults (LFs), which are faults that influence the behavior of each other, such that masking can occur, has proven to be a source for new memory tests, characterized by an increased fault coverage. However, many newly reported fault models have not been investigated from the point-of-view of LFs. This paper presents a complete analysis of LFs, based on the concept of fault primitives, such that the whole space of LFs is investigated and accounted for and validated. Some simulated defective circuits, showing linked-fault behavior, will be also presented. The paper establishes detection conditions along with new tests to detect each fault class. The tests are merged into a single test March SL detecting all considered LFs. Preliminary test results, based on Intel advanced caches, show that its fault coverage is high as compared with all other traditional tests and that it detects some unique faults; this makes March SL very attractive industrially. [ABSTRACT FROM AUTHOR]

Presents an overview of realistic fault models for dual-port memories divided into single-port faults and faults for dual-port memories of computers. Classification of single-port functional fault models; Conditions for detecting two-port faults (2PF); Classification of 2PF tests.

Assesses spot defects in multiport memories resulting in realistic fault models. Classification of spot defects; Discussion on the simulation model and methodology; Details on the functional fault models (FFM); Calculation of the probabilities of occurrence of each FFM.

The Advanced Encryption Standard (AES) is widely recognized as a robust cryptographic algorithm utilized to protect data integrity and confidentiality. When it comes to lightweight implementations of the algorithm, the literature mainly emphasizes area and power optimization, often overlooking considerations related to performance and security. This paper evaluates two of our previously proposed lightweight AES implementations using both profiled and non-profiled attacks. One is an unprotected implementation, and the other one is a protected version using Domain-Oriented Masking (DOM). The findings of this study indicate that the inclusion of DOM in the design enhances its resistance to attacks at the cost of doubling the area. [ABSTRACT FROM AUTHOR]

Advances in materials science and memory devices work in tandem for the evolution of Artificial Intelligence systems. Energy-efficient computation is the ultimate goal of emerging memristor technology, in which the storage and computation can be done in the same memory crossbar. In this work, an analog memristor device is fabricated utilizing the unique characteristics of single-wall carbon nanotubes (SWCNTs) to act as the switching medium of the device. Via the planar structure, the memristor device exhibits analog switching ability with high state stability. The device's conductance and capacitance can be tuned simultaneously, increasing the device's potential and broadening its applications' horizons. The multi-state storage capability and long-term memory are the key factors that make the device a promising candidate for bio-inspired computing applications. As a demonstrator, the fabricated memristor is deployed in spiking neural networks (SNN) to exploit its analog switching feature for energy-efficient classification operation. Results reveal that the computation-in-memory implementation performs Vector Matrix Multiplication with 95% inference accuracy and few femtojoules per spike energy efficiency. The memristor device presented in this work opens new insights towards utilizing the outstanding features of SWCNTs for efficient analog computation in deep learning systems. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various reports within the issue on topics including the simulation of hot carrier injection (HCI)-induced variations of integrated circuit (IC) timings at high level, the relation between low-level single or multiple transients using fast estimation of error probabilities, and an adaptive fault tolerant architecture for multi-core systems.

Summary: The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The Tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field toward practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, the basic aspects of spin-wave computing and individual spin-wave devices are reviewed. The focus is on spin-wave majority gates as they are the most prominently pursued device concept. Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input–output consistency, and fan-out achievement. We argue that spin-wave circuits need to be embedded in conventional complementary metal–oxide–semiconductor (CMOS) circuits to obtain complete functional hybrid computing systems. The state of the art of benchmarking such hybrid spin-wave–CMOS systems is reviewed, and the current challenges to realize such systems are discussed. The benchmark indicates that hybrid spin-wave–CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product. Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers. [ABSTRACT FROM AUTHOR]

The popularity of perpendicular magnetic tunnel junction (pMTJ)-based spin-transfer torque magnetic random access memories (STT-MRAMs) is growing very fast. The performance of such memories is very sensitive to magnetic fields, including both internal and external ones. This article presents a magnetic-field-aware compact model of pMTJ, named the MFA-magnetic tunnel junction (MTJ) model, for magnetic/electrical co-simulation of MTJ/CMOS circuits. Magnetic measurement data of MTJ devices, with diameters ranging from 35 to 175 nm, are used to calibrate an in-house magnetic coupling model. This model is subsequently integrated into our developed compact pMTJ model, which is implemented in Verilog-A. The superiority of the proposed MFA-MTJ model for device/circuit co-design of STT-MRAM is demonstrated by simulating a single pMTJ as well as STT-MRAM full circuits. The design space is explored under PVT variations and various configurations of magnetic fields. [ABSTRACT FROM AUTHOR]

The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor-based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect. [ABSTRACT FROM AUTHOR]

3-D stacked integrated circuit (IC) technology based on through-silicon vias (TSVs) provides numerous advantages as compared to traditional 2-D-ICs. A potential application is memory stacked on logic, providing enhanced throughput, and reduced latency and power consumption. However, testing the TSV interconnects between the two dies is challenging as both memory and logic dies might come from different providers. Currently, no standard exists and the proposed solutions fail to address dynamic and time-critical faults (at speed testing). In addition, memory vendors have not been in favor to put additional design-for-testability structures such as Joint Test Action Group for interconnect testing on their memory devices. This paper proposes a new memory-based interconnect test (MBIT) approach for 3-D memories stacked on logic (e.g., CPUs). A structural approach is used to develop fault models, their detection conditions, and test and diagnosis patterns. The test patterns are applied by read and write instructions to the memory and are validated by a case study where a 3-D memory is assumed to be stacked on a MIPS64 processor. The main benefits of the MBIT approach are: 1) zero area overhead; 2) the ability to detect both static and dynamic faults and perform at speed testing; 3) flexibility in applying any test pattern, as this can be executed by the CPU on the logic die; 4) extreme short test execution time; and 5) the ability to perform interconnect diagnosis. [ABSTRACT FROM AUTHOR]

Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. It investigates two secure Built-In Self-Test (BIST) solutions for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The schemes target high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The first scheme reuses existing FE blocks (for pattern generation and compression) to minimize the area overhead, while the second scheme tests all the FE blocks simultaneously to minimize the test time. The schemes are integrated in FE design and simulated; the results show that for the first test scheme, a SAF fault coverage of 95 % can be realized with no more than 47.1k clock cycles at the cost of a negligible area overhead of only 2.2 %; while for the second test scheme a SAF fault coverage of 95 % can be realized with 3.5k clock cycles at the cost of 18.6 % area overhead. Higher fault coverages are possible to realize at extra cost (i.e., either by extending the test time, or by adding extra hardware, or a combination of both). [ABSTRACT FROM AUTHOR]

A novel type of hardware accelerators called automata processors (APs) have been proposed to accelerate finite-state automata. The bone structure of an AP is a hierarchical routing matrix that connects many memory arrays. With this structure, an AP can process an input symbol every clock cycle, and hence achieve much higher performance compared to conventional architectures. However, the design automation for the APs is not well researched. This article proposes a fully automated tool named APmap for mapping the automata to APs that use a two-level routing matrix. APmap first partitions a large automaton into small graphs and then maps them. Multiple transformations are applied to the automaton by APmap to meet hardware constraints. The experiments on a standard benchmark suite show that our approach leads to around 19% less storage utilization compared to state-of-the-art. [ABSTRACT FROM AUTHOR]

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles. [ABSTRACT FROM AUTHOR]

By their very nature, spin waves (SWs) with different frequencies can propagate through the same waveguide, while mostly interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road toward hardware replication-free parallel data processing. In this article, we take advantage of these features and propose a novel data parallel SW-based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input majority gates are implemented and validated by means of Object-Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and majority implementations, respectively. To get inside on the practical implications of our proposal, we compare the byte-wide gates with conventional functionally equivalent scalar SW gate-based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase-based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold-based detection-based gates. [ABSTRACT FROM AUTHOR]

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fanout capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fanout of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible, proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15 nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires a 12× less area than the 15 nm CMOS MAJ3 gate and that at the gate level, the fanout capability results in 16% area savings, when compared to the state-of-the-art SW majority gate counterparts. [ABSTRACT FROM AUTHOR]

This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area. [ABSTRACT FROM AUTHOR]

This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design. [ABSTRACT FROM AUTHOR]

This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing ( BLS ) (which reflect the degradation of the cell) and the sensing delay ( SD ) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement). [ABSTRACT FROM AUTHOR]

Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar-based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar offers many advantages including scalability, high integration density, nonvolatility, etc. The state-of-the-art for memristor crossbar logic circuit design can only implement simple and small circuits. This paper proposes a mapping methodology of large Boolean logic circuits on memristor crossbar. Appropriate place-and-route schemes, to efficiently map the circuits on the crossbar, as well as several optimization schemes are also proposed. To illustrate the potential of the methodology, a multibit adder and other nine more complex benchmarks are studied; the delay, area and power consumption induced by both crossbar and its CMOS control part are evaluated. [ABSTRACT FROM AUTHOR]

Extreme-scale computer systems take advantage of large arrays of general-purpose multicore processors coupled with specialized manycore accelerators. In order to support complex applications and correctly feed such processing elements, increasingly larger memory cores are integrated at different levels of the hierarchy. However, the adoption of increasingly aggressive manufacturing processes makes the memory sub-system particularly sensitive to faults. Error correcting codes (ECCs) allow the memory to recover from faults at run-time without interfering with the application execution. However, due to the loss of performance introduced every time an error must be corrected, the persistence of faults requires a more radical repair approach in which faulty cells are physically replaced by spare ones. Memory redundancy analysis (MRA) algorithms are used to drive the allocation process of spare resources. Many one-dimensional and two-dimensional MRAs have been proposed, but tools for evaluating their recovering capability are still not well established. This paper presents SIERRA, a simulation environment for precisely evaluating the repair efficiency of an MRA considering different fault signatures and faulty memory configurations. Our simulation engine provides a precise estimation of the MRA quality by analyzing the behavior of the MRA on several faulty memory configurations. To this end, different parameters such as the area of the memory blocks and the defect density are taken into account. The evaluation of the quality of an MRA takes into account its repairing capability, the power consumption derived from its execution, and the area overhead. Thanks to the use of a database for storing information, our tool is able to speed-up the simulation process by distributing it among several nodes. All these features make SIERRA essential in supporting the design of next-generation high-performance computers. [ABSTRACT FROM AUTHOR]

Fault injection attacks are a threat to all digital systems, especially to the ones conducting security sensitive operations. Recently, the strategy of observing the instruction flow to detect attacks has gained popularity. In this paper, we provide a comparative study between three hardware-based techniques (i.e., recurrent neural network (RNN), content addressable memory (CAM), and Bloom filter (BF)) that detect fault attacks against software RSA decryption. After conducting experiments with various fault models, we observed that the CAM provides the best detection rate, the RNN provides the most software/application flexibility, and the BF is a middle ground between the two. Regardless, all of them exhibit robustness against faults targeted at them, and obtain a very high detection rate when faults change instructions altogether. This affirms the validity of monitoring the integrity of the instruction flow as a strong countermeasure against any type of fault attack. [ABSTRACT FROM AUTHOR]

Caches form a key feature of modern processors as they help to improve memory access timing by exploiting temporal and spatial data locality. However, the timing differences between cache hits and misses may lead to security vulnerabilities as they can be exploited by logical side channels. In this paper, we propose an innovative and coherent verification methodology to formally verifies cache designs against the potential existence of cache side channel vulnerabilities. Our methodology has been applied to three different cache models, i.e., a conventional cache, a static partitioned cache and a dynamic partitioned cache. The vulnerabilities of these caches have been evaluated using 28 different cache attack types. Results show that our proposed verification method can be applied successfully in verifying whether a cache is vulnerable to side channel attacks or not. • Formal verification • Cache Vulnerabilities • Security requirement • Security • Cache verification template [ABSTRACT FROM AUTHOR]