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We demonstrate a nonvolatile electrically erasable programmable read-only memory device using gold nanoparticles as charge storage elements deposited at room temperature by chemical processing. The nanoparticles are deposited over a thermal silicon dioxide layer that insulates them from the device silicon channel. An organic insulator deposited by the Langmuir–Blodget technique at room temperature separates the aluminum gate electrode from the nanoparticles. The device exhibits significant threshold voltage shifts after application of low-voltage pulses (<=±6 V) to the gate and has nonvolatile retention time characteristics. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Presents a study that investigated the electrical properties of buried oxide-silicon interface. Information on the separation by implanted oxygen and deep level transient spectroscopy techniques; Experimental details; Results and discussion.

In this work, we report on the structural and electrical properties of oxide–nitride–oxide (ONO) structures that were formed by low-energy silicon or nitrogen implantation into oxide–nitride stacks. In particular ON stacks (2.5 nm/6 nm) were formed on n-type Si substrates, further implanted with 1 keV Si or N to a fluence of 10 16 ions/cm 2 , and finally wet oxidized at 850 °C for 15 min. TEM imaging showed that the thickness of the blocking oxide layer, formed during wet oxidation, strongly depends on the implanted species. Charging characteristics revealed that Si implanted stacks can trap either electrons or holes resulting to a memory window as large as 8.5 V. In turn N implanted stacks can trap only electrons with a corresponding memory window of 4 V. Room-temperature charge retention measurements showed that the electron loss rate is faster in samples implanted with Si (∼0.32 V/decade) compared to N-samples (∼0.1 V/decade). The 10-year extrapolated memory windows were 1.7 and 2.5 V for Si and N-implanted devices, respectively. Retention measurements within the temperature range of 25–150 °C indicate that the Si implanted stacks exhibit a thermally activated retention, while N-samples showed a temperature independent behavior. These results are mainly attributed to the different nature of traps generated by ion implantation and wet oxidation processing. [ABSTRACT FROM AUTHOR]

In this paper, we review the fabrication and the electrical characteristics of metal-insulator-semiconductor (MIS) devices with semiconductor quantum dots (QD) embedded into the gate dielectric. Our results originate from experiments performed the last decade and cover Si QDs realized by low-energy ion-beam synthesis (IBS) as well as GaN QDs formed by molecular beam deposition (MBD). Besides the basic capacitance-to-voltage ( C- V) and current-to-voltage ( I- V) characterization, the memory properties of the fabricated MIS devices were investigated in terms of memory window under pulse operation and charge retention. The optimization of Si-QD memory cells is reviewed and a methodology for both the extraction of various device parameters and the identification of mechanisms governing the charge loss process are presented. GaN QDs, which exhibit negative conduction band-offset with respect to the Si conduction band, offer an interesting alternative to Si QDs as discussed herein based on our investigations of GaN-QD capacitors fabricated by a complementary-metal-oxide-semiconductor (CMOS) compatible process. [ABSTRACT FROM AUTHOR]

Gallium nitride quantum dots (QDs) were investigated as discrete charge storage nodes embedded in the gate dielectric of metal-oxide-semiconductor (MOS) capacitors. The GaN QDs were formed on top of 3.5 nm-thick SiO2/n-Si(001) substrates by radiofrequency plasma-assisted molecular beam deposition. The MOS structures were studied by transmission electron microscopy. Deposition dose was determined as a critical process parameter to obtain two dimensional arrays of discrete QDs. The memory window width, programming speed, and charge retention time were evaluated for GaN QD devices with different deposition doses. All devices showed enhanced electron trapping leading to significant memory windows. Charge retention measurements, at room temperature, revealed that the sample with the lowest concentration of QDs exhibits a low charge loss with a significant extrapolated programming window after 10 yrs. The present study not only demonstrates GaN QD embedded SiO2 structures fabricated by a fully complementary metal oxide semiconductor compatible method but also points out that these structures are promising for the realization of nanofloating gate non-volatile memory devices. [ABSTRACT FROM AUTHOR]

Abstract: Structural and electrical properties of ALD-grown 5 and 7nm-thick Al2O3 layers before and after implantation of Ge ions (1keV, 0.5–1×1016 cm−2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ∼5nm inside the implanted Al2O3 layers after annealing at 800°C for 20min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers. [Copyright &y& Elsevier]

Abstract: This work presents an alternative method for the formation of the top oxide in oxide-nitride-oxide structures. The method utilizes low-energy (1 keV) Si ion implantation into thin oxide-nitride stacks, followed by low temperature wet oxidation. Transmission electron microscopy examination clearly indicates the formation of a three-layer structure, verified also by Time-of flight secondary ion mass spectrometry. The electrical characteristics of the oxide-nitride-oxide stacks exhibit strong trapping effects and excellent retention characteristics resulting to a 1.5 V 10-year memory window at 125 °C. [Copyright &y& Elsevier]

Abstract: This paper examines the influence of channel edge effects on the memory performance of shallow-trench-isolated Si-nanocrystal single-MOSFET memory cells. The devices were fabricated in a manufacturing environment using a process flow and design rules based on a 0.15μm Flash-EEPROM technology. The Si-nanocrystals were generated in the gate oxide by low-energy (1keV) ion-beam-synthesis. For 10×10μm2 and 0.9×0.6μm2 (W × L) devices, parasitic transistors formed at the channel edges lead to a “subthreshold hump” in the transfer characteristics. Beyond this current hump, the device transfer characteristics correspond to that of the intrinsic transistor formed in the central part of the channel. Memory testing reveals that the parasitic transistors can be programmed or erased but exhibit memory characteristics significantly different than that of the intrinsic transistor. Hence, the extracted memory windows strongly depend on the source-drain current used for threshold-voltage evaluation when applying the constant current method. In addition to the latter method, the more accurate transconductance change method is herein applied to describe the memory behavior of the intrinsic and parasitic transistors in a more comprehensive way. Finally, while no “subthreshold hump” appears in the transfer characteristics of 0.16×0.3μm2 transistors, it is shown that the parasitic transistors remain active and their operation dominates the memory behavior of the devices. As emphasized herein the parasitic transistors affect drastically the memory performance of the intended devices and this detrimental effect could constitute a technological issue towards the integration of nanocrystal floating-gate in conventional memory architecture. [Copyright &y& Elsevier]

Abstract: In this communication, we report on the realization of low-temperature processed Electrically Erasable Programmable Read-Only Memory (EEPROM) like device with embedded gold nanoparticles. The realization is based on the fabrication of a V-groove SiGe Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir–Blodgett (LB) technique. Such structures were processed at a temperature lower than 400°C. The electrical characteristics of the final hybrid Metal Insulator Semiconductor FET (MISFET) memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented. [Copyright &y& Elsevier]

Abstract: Nanoparticle memories have made their point during last years as a possible solution to overcome the scaling issue of electronic non-volatile memories. Ultimately, we are looking for nanoparticle memories to significantly decrease the voltage needed to write/erase the memory without compromising its retention characteristics. Several approaches have been reported for semiconductor nanoparticle formation using techniques such as chemical vapor deposition, molecular beam epitaxy or sputtering. In the present review emphasis is placed on a silicon nanoparticle memory resulting from low-energy ion implantation of silicon within a thin oxide layer and subsequent annealing. This process allows for the formation of a two-dimensional array of silicon nanoparticles within the gate oxide in one processing step making the process attractive for CMOS integration. Material issues related with ion implantation energy, dose and annealing ambient for optimum device performance are addressed. As an alternative to semiconductor nanoparticles, metallic nanoparticles have been investigated since they have the potential for more versatile engineering of energy barriers that would allow improved data retention for memory devices operating at low voltages. Processing approaches for metallic nanoparticle formation are addressed and corresponding memory device performance is discussed for the particular case of room temperature deposited metallic nanoparticles by chemical methods. [Copyright &y& Elsevier]

Abstract: A process scheme for the fabrication of a low temperature SiGe V-groove MOSFET is demonstrated. The transfer and output characteristics show promising results for the device performance. The source/drain resistance and the quality of the gate insulator/SiGe channel must be optimized for device operation improvement. [Copyright &y& Elsevier]

Si-nanocrystal memory devices aiming at low-voltage non-volatile memory applications are explored. The devices consist of a single metal-oxide-semiconductor field-effect-transistor with silicon nanocrystals fabricated through ultra-low-energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing. Process issues like boron contamination and parasitic currents that affect the threshold voltage and transfer characteristics of the intended devices are discussed in terms of device structure, process parameter and device simulation. It is shown that these issues can be overcome under appropriate process modifications. Threshold shift of about 2 V are obtained for a 10 ms +9 V/-9 V pulse regime where both electron and hole trapping occur. Neither degradation, nor drift in memory window is detected after 1.5 × 106 10 ms +9 V/-9 V cycles. Charge retention measurements reveal that the de-trapping mechanism of stored holes is faster than that of trapped electrons and independent on the temperature. Memory operation with reduced hole trapping, herein demonstrated for a 10 ms +9 V/-7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 °C, should be preferred for long non-volatile retention of years. [Copyright &y& Elsevier]

We have fabricated a hybrid non-volatile gold nanoparticle floating-gate memory metal insulator semiconductor field effect transistor (MISFET) device combining silicon technology and organic thin film deposition. The nanoparticles are deposited by chemical processes at room temperature over a 5 nm thermal silicon dioxide layer. A multi-layer organic insulator (cadmium arachidate) deposited by the Langmuir–Blodgett technique at room temperature covers the nanoparticle layer and separates it from an Al gate electrode. Charge injection/rejection into the nanoparticles takes place by applying different voltage pulses (less than ±6 V) to the gate electrode, resulting in significant threshold-voltage shift. Charge retention measurements reveal that the device has non-volatile behavior. [Copyright &y& Elsevier]

Recent fabrication issues encountered during the synthesis of silicon nanocrystals in thin SiO2 films by the technique of ultra-low energy ion implantation and subsequent thermal treatment (ULE-IBS) are presented. The effects of charge neutralization of the implanted species, energy contamination and post-implantation cleaning process on the electrical and structural properties of the processed oxides are described, with emphasis upon the technological options to control them. While much research is still required for industrial exploitation of ULE-IBS in the fabrication of competitive and reproducible memory structures, promising results for prototype devices aiming at low-voltage non-volatile memory applications have been obtained and are here reported. [Copyright &y& Elsevier]

The electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals obtained by low-energy ion beam implantation and subsequent annealing have been investigated through capacitance and current–voltage measurements of MOS capacitors. The effects of the implantation energy (range: 0.65–2 keV), annealing temperature (950–1050 °C) and injection oxide characteristics on charge injection and storage are reported. It is shown that the implantation energy allows for a fine control of the memory window characteristics, and various device options are possible including memory operation with charge injection at low gate voltages. [Copyright &y& Elsevier]

Abstract: The fabrication at room-temperature of thin (<8nm) silicon oxide films has been achieved, in a high-density helicon plasma source reactor using Ar/O2 mixture, exhibiting relatively low concentration of fixed oxide and interface charges, after annealing. The developed plasma oxidation process was employed in order to fabricate SOI-MOSFETs at low thermal budget with competitive operating characteristics. [Copyright &y& Elsevier]

An alternative method for the formation of the top oxide in oxide-nitride-oxide dielectric stacks is proposed. This method combines low-energy (1 keV) silicon ion implantation into a thin nitride-oxide stack and subsequent low-temperature wet oxidation (850 °C for 15 min). Transmission electron microscopy shows that for an implanted dose of 1.5×1016 Si cm-2, an 8-nm-thick silicon oxide layer develops on the surface of the nitride-oxide stack. Time of flight secondary ion mass spectrometry reveals: (1) transformation of the implanted silicon nitride to an oxygen-rich-silicon nitride layer and (2) pilling up of nitrogen atoms at the bottom silicon/oxide-substrate interface. The resulting oxide-nitride-oxide stack exhibits strong charge storage effects and excellent charge retention properties leading to a 1.5 V, 10 yr extrapolated memory window at 125 °C. These results suggest that the proposed fabrication route may lead to gate dielectric stacks of substantial potential impact for mainstream nitride-based memory devices. [ABSTRACT FROM AUTHOR]

Presents a study which developed a method for the characterization of the SOI separation by implanted oxygen oxide. Experimental details; Results; Conclusion.

In this work we examine the high temperature charge retention characteristics of modified SONOS (polySi–oxide–nitride–oxide–Si) capacitors. The modified SONOS structures were synthesized by Si low-energy implantation (1 keV) into oxide–nitride (ON) stacks, followed by a wet oxidation step. The retention studies were conducted within the temperature range of 50 to 180 °C after setting the capacitor to an excess electron state of ΔV FB of 3 V. The reference ONO capacitor exhibits a complex behavior which consists of an initial fast discharge rate of 0.1 V/decade which switches to a lower and temperature independent rate of 0.06 V/decade when the ΔV FB reaches 2.86 V. In turn, the implanted and wet oxidized ONO shows a temperature dependent charge decay rate which varies from 0.07 V/decade at 30 °C, to 0.18 V/decade at 180 °C. The retention data have been analytically solved using the Wang–White model. The results showed that the nitride trap distribution of the implanted and wet oxidized sample differs clearly from that of the standard stoichiometric nitride. This is attributed to ion induced structural damage in combination with the wet oxidation which increases the distribution profile at deeper trap energies. [ABSTRACT FROM AUTHOR]

• The role of a 3 nm Al 2 O 3 on top of stoichiometric LPCVD SiN x MIS RRAM cells is investigated. • The devices can be SET at different resistance levels by varying the I CC. • SET/RESET voltages are higher compared to the reference sample, corresponding to the voltage drop on the Al 2 O 3. • A compact model can be successfully used to simulate the I-V curves of our devices in circuit level designs. • Impedance spectroscopy measurements revealed that the conduction in SiN x is mostly governed by trap-to-trap tunneling mechanisms. The role of a 3 nm Al 2 O 3 layer on top of stoichiometric LPCVD SiN x MIS RRAM cells is investigated by using various electrical characterization techniques. The conductive filament formation is explained, and a compact model is used to fit the current–voltage curves and find its evolution during each operation cycle. The conduction in SiN x is also studied. [ABSTRACT FROM AUTHOR]

In this work we examine the structural and electrical properties including the memory performance of Al 2 O 3 /Si 3 N 4 /SiO 2 dielectric stacks implanted with low-energy nitrogen ions and subsequently thermal annealed at 850 or 1050 °C for 15 min. X-ray photoelectron spectroscopy reveals that the concentration and the chemical state of the nitrogen atoms within the Al 2 O 3 layer depends on the post-implantation annealing (PIA) temperature. Memory testing, performed on platinum gate capacitors, shows that charge retention of the programmed states is significantly improved for the high-temperature PIA samples as compared to the non-implanted samples. While such an improvement is not detected for the low-temperature PIA samples, the latter exhibit enhanced hole charging and thus, increased erase efficiency. Overall, our results suggest that the transport properties which control the erase and the retention characteristics of the blocking Al 2 O 3 layer can be tailored by nitrogen implantation and the PIA conditions and can be used for memory performance optimization. [ABSTRACT FROM AUTHOR]

Abstract: The dependence of the various possible physical mechanisms, governing electron flow in planar metal- molecular layer-metal junctions, upon voltage bias and temperature is investigated in this work. A molecular self-assembled monolayer containing inorganic tungsten-polyoxometalate molecules is studied. These molecules are interesting for molecular memory applications due to their redox properties. Low temperature (T <150K) conduction is attributed to indirect tunneling; the effective tunneling barrier decreases with the rise of temperature due to the variation of available electronic states in the metal electrodes. Upon further increase of temperature, hopping arises as conduction mechanism and actually dominates for temperatures higher than 200K. The hopping activation energies found are several tenths of meV. The transition between conduction mechanisms depends also on the electrode distance. [Copyright &y& Elsevier]

Abstract: We report on the development of hybrid organic/inorganic thin-film transistors using regioregular poly-3-hexylthiophene (P3HT) semiconductor material deposited by means of the solid-phase Laser Induced Forward Transfer (LIFT) technique. P3HT pixels were LIFT-printed onto Au/Ti source and drain electrodes formed on silicon dioxide/p+-type Si substrate. Deposition of the P3HT pixels was investigated as a function of the laser fluence using donor substrates with and without a dynamic release layer. Device electrical characterization reveals efficient field-effect action of the bottom gate on the organic channel. The transfer I DS–V GS characteristics exhibit well-defined sub-threshold, linear and saturation regimes designating LIFT as a promising technique for hybrid organic/inorganic transistor technology. [Copyright &y& Elsevier]

The structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals are reported fabricated by low-energy silicon implantation and with subsequent annealing in inert and diluted oxygen. Thermal treatment in diluted oxygen increases the thickness of the control oxide, does not affect significantly the size of the nanocrystals, and improves the integrity of the oxide. As a result, strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of MOS capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen permits the fabrication of low-voltage nonvolatile memory devices. [Copyright &y& Elsevier]

We analyze a method to selectively grow straight, vertical gallium nitride nanowires by plasma-assisted molecular beam epitaxy (MBE) at sites specified by a silicon oxide mask, which is thermally grown on silicon (111) substrates and patterned by electron-beam lithography and reactive-ion etching. The investigated method requires only one single molecular beam epitaxy MBE growth process, i.e., the SiO2 mask is formed on silicon instead of on a previously grown GaN or AlN buffer layer. We present a systematic and analytical study involving various mask patterns, characterization by scanning electron microscopy, transmission electron microscopy, and photoluminescence spectroscopy, as well as numerical simulations, to evaluate how the dimensions (window diameter and spacing) of the mask affect the distribution of the nanowires, their morphology, and alignment, as well as their photonic properties. Capabilities and limitations for this method of selective-area growth of nanowires have been identified. A window diameter less than 50 nm and a window spacing larger than 500 nm can provide single nanowire nucleation in nearly all mask windows. The results are consistent with a Ga diffusion length on the silicon dioxide surface in the order of approximately 1 μm. [ABSTRACT FROM AUTHOR]

The effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported. Annealing in diluted oxygen increases the thickness of the control oxide, improves the integrity of the oxide and narrows the size distribution of the nanocrystals without affecting significantly their mean size (∼2 nm). Strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of metal-oxide-semiconductor capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen allows for the fabrication of improved low-voltage nonvolatile memory devices. [ABSTRACT FROM AUTHOR]

• Stoichiometric SiNx layers are doped with Si atoms. • Ultra-low energy ion implantation and annealing at different temperatures was used. • Detailed material and memory cells characterization is performed. • DC current–voltage and impedance spectroscopy measurements carried out. • The role of doping in dielectric properties of the nitride films are enlighten. • Room temperature retention of resistive states are also presented. Stoichiometric SiN x layers (x = [N]/[Si] = 1.33) are doped with Si atoms by ultra-low energy ion implantation (ULE-II) and subsequently annealed at different temperatures in inert ambient conditions. Detailed material and memory cells characterization is performed to investigate the effect of Si dopants on the switching properties and performance of the fabricated resistive memory cells. In this context extensive dc current–voltage and impedance spectroscopy measurements are carried out systematically and the role of doping in dielectric properties of the nitride films is enlightened. The dc and ac conduction mechanisms are investigated in a comprehensive way. Room temperature retention characteristics of resistive states are also presented. [ABSTRACT FROM AUTHOR]

The effect of thermal treatments in nitrogen-diluted oxygen on the structural characteristics of two-dimensional arrays of Si nanocrystals (NCs) fabricated by ultralow-energy ion implantation (1 keV) in thin silicon dioxide layers is reported. The NC characteristics (size, density, and coverage) have been measured by spatially resolved electron-energy-loss spectroscopy by using the spectrum-imaging mode of a scanning transmission electron microscope. Their evolution has been studied as a function of thermal treatment duration at a temperature (900 °C) below the SiO2 viscoelastic point. An extended spherical Deal-Grove [J. Appl. Phys. 36, 3770 (1965)] model for self-limiting oxidation of embedded silicon NCs has been carried out. It proposes that the stress effects, due to oxide deformation, slow down the NC oxidation rate and lead to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results. Soft oxidation appears to be a powerful way for manipulating the NC size distribution and surface density. [ABSTRACT FROM AUTHOR]

In silicon nanocrystal based metal-oxide-semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the" injection distance" can be achieved by varying the Si+ ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy (XTEM) method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values (2 nm) can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM are compared with Monte-Carlo simulations of the implanted Si profiles taking into account dynamic target changes due to ion implantation, ion erosion, and ion beam mixing. This combination of experimental and theoretical studies gives a safe explanation regarding the unique technological route of obtaining Si nanocrystals at distances smaller than 5 nm from the channel: the formation of nanocrystals requires that the interface mixing due to collisional damage does not overlap with the range profile to the extent that there is no more a local maximum of Si excess buried in the SiO 2 layer. [ABSTRACT FROM AUTHOR]

• A crossbar array of silicon nitride resistive memories was fabricated on SOI. • Multi-Level-Cell capabilities were demonstrated through DC measurements and model. • A comprehensive analysis of the MRL gates' design and optimizations were done. In this work, the fabrication of crossbar arrays of silicon nitride resistive memories on silicon-on-insulator substrate and their utilization to realize multi-rationed logic circuits are presented. Typical electrical characterization of the memristors revealed their ability of multi-state operation by the presence of 12 well separated resistance levels. Through a dedicated modeling and fitting procedure of these levels, a reconfigurable logic based on memristor rationed logic scheme is designed and a crossbar integration methodology was proposed. Finally, several circuitry aspects were simulated in SPICE with a silicon nitride SOI crossbar array calibrated model and power optimization prospects were discussed. [ABSTRACT FROM AUTHOR]

Reference-guided DNA sequencing and alignment is an important process in computational molecular biology. The amount of DNA data grows very fast, and many new genomes are waiting to be sequenced while millions of private genomes need to be re-sequenced. Each human genome has 3.2B base pairs, and each one could be stored with 2 bits of information, so one human genome would take 6.4B bits or ∼760MB of storage (National Institute of General Medical Sciences, n.d.). Today's most powerful tensor processing units cannot handle the volume of DNA data necessitating a major leap in computing power. It is, therefore, important to investigate the usefulness of quantum computers in genomic data analysis, especially in DNA sequence alignment. Quantum computers are expected to be involved in DNA sequencing, initially as parts of classical systems, acting as quantum accelerators. The number of available qubits is increasing annually, and future quantum computers could conduct DNA sequencing, taking the place of classical computing systems. We present a novel quantum algorithm for reference-guided DNA sequence alignment modeled with gate-based quantum computing. The algorithm is scalable, can be integrated into existing classical DNA sequencing systems and is intentionally structured to limit computational errors. The quantum algorithm has been tested using the quantum processing units and simulators provided by IBM Quantum, and its correctness has been confirmed. [Display omitted] • Quantum computers are expected to be involved in DNA sequencing acting as quantum accelerators. • Novel quantum algorithm for reference-guided DNA sequence alignment modeled with gate-based quantum computing. • The quantum algorithm has been tested using the quantum processing units and simulators provided by IBM Quantum. • The quantum algorithm can align sequences very fast and be applied in any assay performed with next generation sequencing. [ABSTRACT FROM AUTHOR]

De novo DNA sequence assembly is based on finding paths in overlap graphs, which is a NP-hard problem. We developed a quantum algorithm for de novo assembly based on quantum walks in graphs. The overlap graph is partitioned repeatedly to smaller graphs that form a hierarchical structure. We use quantum walks to find paths in low rank graphs and a quantum algorithm that finds Hamiltonian paths in high hierarchical rank. We tested the partitioning quantum algorithm, as well as the quantum algorithm that finds Hamiltonian paths in high hierarchical rank and confirmed its correct operation using Qiskit. We developed a custom simulation for quantum walks to search for paths in low rank graphs. The approach described in this paper may serve as a basis for the development of efficient quantum algorithms that solve the de novo DNA assembly problem. [ABSTRACT FROM AUTHOR]

Abstract: The effect of the material of the metal plates (Au, Ta, W) and exposure to a high-power blue laser on the memristive characteristics of metal-insulator-semiconductor (MIS) capacitors with a Si3N4 film 6 nm thick fabricated on the basis of n+-Si is studied. It is shown that bipolar switching by the current appears only in capacitors with Au. The causes of the absence of bipolar switching in capacitors with Ta and W are explained. The switching of capacitors with Ta by the current and light and the photomemory effect are detected. It is shown that, despite the high doping level of the semiconductor substrate, it decreases the MIS memristor response rate due to a high density of surface states localized at the Si3N4/n+-Si interface. However, illumination allows a significant increase in the response rate due to a decrease in the semiconductor resistivity. The surface state densities are determined. To improve the frequency characteristics of MIS memristors, it is necessary to achieve a low surface state density. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memory (RRAM) with a structure Au/Ti/TiO 2− x /Au demonstrated a clear bipolar resistive switching behavior without the necessity of an initial electroforming process. The titanium oxide (TiO 2− x ) thin film was deposited by reactive RF magnetron sputtering at room temperature in a controlled oxygen/argon ambient. The high density of oxygen vacancies within the film (induced by the low oxygen content) is an essential component for the formation of conducting filaments and demonstration of DC or nanosecond pulsed resistance switching, but also impose limitations for the conduction behavior of the high resistance state. Conductive Atomic Force Microscopy (C-AFM) was then employed in order to investigate the nanoscale electrical properties of our device. In situ current distribution during the SET process disclosed possible formation of conducting filaments while DC sweeping bias voltage revealed an OFF/ON switching ratio of about 200. We have also demonstrated that by using C-AFM both a low resistance state and a high resistance state can be written by bipolar voltage application imaged by corresponding patterns on the TiO 2− x current image, suggesting that oxygen ions movement at the Pt-Ir coated tip/TiO 2− x interface plays a critical role in the resistive switching phenomenon and thus correlating the macroscopic characteristics of our device with its microscopic origins. Nanoscale resistance switching is also demonstrated by programming distinct patterns on the device's current image. [ABSTRACT FROM AUTHOR]

• Silicon nitride was used as resistive switching in a MIS memristor structure on heavily doped SOI substrates. • The active electrode was Cu allowing for Top electrode. • AC impedance and current-voltage sweep measurements revealed higher series on SOI compared to bulk Si substrate. • Low-frequency noise measurements at low resistance state revealed the silicon nitride traps as main noise source. • Devices on SOI exhibited self-compliance characteristics as revealed by I - V sweeps and AC impedance measurements. Several resistive memory technologies (RRAMs) are prominent, but few are fulfilling the requirements for CMOS integration and meet the commercialization standards. In this work, the fabrication and electrical characterization of a fully compatible CMOS process on SOI substrate of 1R silicon SiN-based resistance switching (RS) MIS devices is presented. The RS characteristics are compared with the same devices previously fabricated on bulk silicon. [ABSTRACT FROM AUTHOR]

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories. [ABSTRACT FROM AUTHOR]

Abstract: An attractive alternative for extending the scaling of Flash-type memories is to replace the conventional floating gate (a poly-Si layer) by laterally isolated floating nodes in the form of nanoparticles. This floating-gate concept has led to the emergence of the so-called nanocrystal (NC) memories which have the potential of operating at lower voltages and higher speeds compared to the conventional non-volatile memories (NVMs) without compromising the criterion of non-volatility. NC memories also offer other advantages like a better immunity to the crosstalk effect arising from the floating-gate coupling of closely spaced adjacent cells and an increased design flexibility from which quantum confinement phenomena can be judiciously exploited for enhanced memory functionality. Among the different technological routes explored in the last few years for generating nanocrystals in the gate insulator of MOS devices, two major techniques have been utilized, namely deposition in vacuum and ion beam synthesis. During the last decade, we have extensively explored the ultra-low-energy ion-beam-synthesis (ULE-IBS) technique to produce single planes of Si-NCs in very thin (5–10nm) insulator layers. This review summarizes more than 10 years of research efforts we and other groups have dedicated to the fabrication of NCs memories using this original technique. By exploiting the flexibility of the ULE-IBS route, Si-NCs single-transistor NVM cells using “classical” gate oxides (SiO2) have been successfully realized. More recently, advanced dielectric stacks employing high-κ dielectric (HfO2) as tunnel oxide and SiN as control oxide and host matrix for Si and Ge-NCs, have been fabricated and show promising performance for low-voltage operating-NVM devices. Particular emphasis is placed herein on material science issues such as anomalous and controlled oxidation processes. While much research is still needed for making reliable and competitive NC NVMs, our systematic investigations based on the ULE-IBS option demonstrate that a tight control and understanding of the properties of NCs memory cells can be achieved, provided that deep structural characterization is coupled to electrical studies. [Copyright &y& Elsevier]

In this paper, the characteristics of silicon nanocrystals used as charge trapping centers in memory devices are examined using the two-level charge pumping (CP) technique performed as a function of frequency and energy filtered transmission electron microscopy (EFTEM). The parameters extracted from the two methods such as the depth location, density and effective diameter of the nanocrystals are in good quantitative agreement. These results validate the charge pumping approach as a non-destructive powerful technique to access most of the properties of nanocrystals embedded in dielectrics and located at injection distances from the substrate surface not limited to the direct tunneling regime. [ABSTRACT FROM AUTHOR]

Abstract: The present paper focuses on the effect of the implantation energy in the fabrication of pockets of silicon nanocrystals (Si-NCs) by stencil-masked ultra-low-energy ion-beam-synthesis (ULE-IBS). Si ion implantation was carried out into 10nm SiO2 layers using energies ranging from 1 up to 3keV and a fluence of 1×1016 Si+/cm2. After mask removal the samples are furnace annealed at 1050°C for 30min under N2 atmosphere. Control of Si-NCs characteristics was examined as a function of the stencil aperture size. Then, different patterns of Si-NCs pockets were synthesized such as squares and gratings of line arrays. Photoluminescence (PL) spectroscopy under a confocal microscope was employed to map the NCs pocket arrays. These PL images were found to perfectly mimic the mask geometry. A change in PL intensity and a blueshift of the PL energy peak were observed near the edge of the pockets. These local changes were attributed to both a smaller size and a higher density of Si-NCs in such areas, probably due to a local decrease of the implanted fluence. AFM measurements of the oxide swelling as a function of the elaboration conditions were combined to PL results to evaluate the real implanted fluence, which is lower than the nominal one. The implanted fluence was also found to decrease with decreasing aperture size, until a threshold for the absence of Si-NCs formation is reached in sub-micron patterns. [Copyright &y& Elsevier]

Abstract: In this work we examine the influence of thermal oxidation on the electrical characteristics of ultra-thin strained silicon layers grown on relaxed Si0.78Ge0.22 substrates under moderate to high thermal budget conditions in N2O ambient at 800°C. The results reveal the presence of a large density of interfacial traps which depends on the oxidation process. As long as the strained silicon layer remains between the growing oxide and the underlying Si0.78Ge0.22 layer, the density of interface traps increases with increasing oxidation time. When the oxidation process consumes the s-Si layer the interface state density undergoes a significant reduction of the order of 40%. This experimental evidence signifies that the strained silicon–Si0.78Ge0.22 interface is a major source of the measured interfacial defects. This situation can be detected only when the front SiO2-strained silicon interface and the rear strained silicon–Si0.78Ge0.22 interface are in close proximity, i.e. within a distance of 5nm or less. Finally, the influence of the material quality deterioration—as a result of the thermal treatment—to the interfacial properties of the structure is discussed. [Copyright &y& Elsevier]

We report on proton radiation effects on Si-nanocrystal (Si-NCs) MOS capacitors and nMOS transistors aiming at non-volatile memory applications. Irradiation experiments were conducted on NC MOS capacitors using protons of 1.5 MeV and 6.5 MeV and on NC nMOS transistors using protons of 1.5 MeV. The range of doses investigated was ~1 to ~100 Mrad(SiO2). A 2-D layer of Si NCs with ~ 3 nm mean diameter and 1012 cm-2 surface density was successfully achieved by low-energy (1 keV) ion-beam-synthesis in thin SiO2 layers. After irradiation, programmed capacitors are found to undergo bit flip while programmed transistors are not. Charge retention measurements at room temperature for the write and erase states of irradiated and non-irradiated samples reveal that a significant memory window exists at an extrapolated time of ten years even after an irradiation dose as high as 120 Mrad (SiO2). The flat-band decay rate of the erase state in NC MOS capacitors does not depend on the irradiation-dose while the opposite occurs for the write state which is found to be directly dependent on Dit values after irradiation. These results clearly indicate that NC Non-Volatile Memories (NVM) are promising radiation tolerant devices. [ABSTRACT FROM AUTHOR]

Abstract: We report on proton radiation tolerance of Si-nanocrystal (Si-NCs) MOS structures aiming at non-volatile memory applications. Si-NCs were formed by low-energy (1keV) ion-beam-synthesis within a 9nm thick SiO2 layer. A 2-D layer of Si-NCs with 3nm mean diameter and 1012 cm−2 surface density was successfully achieved. After fabrication of Al capacitors, samples with and without Si-NCs were 1.5 and 6.5MeV proton were irradiated at doses ranging from 1Mrad (SiO2) to 120Mrad (SiO2). Significant irradiation-dose-dependent shifts are detected in the C–V curves of the NC-MOS cells and programmed cells are found to undergo bit flip. Despite the above, the attainable memory windows after write/erase operations remain unchanged. Retention time characteristics at room temperature for the write and erase states of irradiated and non-irradiated samples reveal that even after an irradiation dose as high as 120Mrad (SiO2) the devices still exhibit long time charge storage behavior. We observe that the erase state flat-band voltage decay rate does not depend on the irradiation-dose while the opposite happens for the write state flat-band voltage decay rate which is found to be directly dependent on D it values giving insight to the physics of the discharging mechanisms. [Copyright &y& Elsevier]

Abstract: This work combines plasma doping implantation (PLAD) with laser annealing using excimer laser, for the formation of ultra-shallow junctions. For that purpose, high dose BF3 was implanted in n-type silicon wafers using PLAD. The as implanted material was investigated by high resolution TEM, measured by SIMS and simulated by Monte-Carlo codes. Subsequently, the samples were annealed using a KrF laser source at 248nm with a pulse duration 20ns and different fluence values. Laser annealing completely recrystallizes the amorphous layer as monitored by TEM measurements, fully activates the dopants achieving low sheet resistance values as shown by Van der Pauw measurements and results in box-shaped dopant profiles with movement less than 10nm at the junction depth as measured using SIMS. [Copyright &y& Elsevier]

Abstract: In nanocrystal (nc) metal-oxide-semiconductor (MOS) memory structures, a fine control of nc location and population is required for pinpointing the optimal device architectures. In this work, we show how to manipulate and control the depth-position, size and surface density of two dimensional (2D) arrays of Si ncs embedded in thin (<10nm) SiO2 layers, fabricated by ultra-low energy (typically 1keV) ion implantation and subsequent annealing. The influence of implantation and annealing conditions on the nc characteristics (e.g. size, density) and the charge storage properties of associated MOS structures is reported with particular emphasis upon the effect of annealing in N2-diluted–O2 gas mixture. The latter annealing conditions restore the integrity of the oxide and allow for the fabrication of non-volatile memory devices operating at low-gate voltages. Annealing in diluted oxygen has also an effect on the population of silicon ncs. Their evolution has been studied as a function of the annealing duration under N2 +O2 at 900°C. An extended spherical Deal–Grove model for the self-limiting oxidation of embedded Si ncs has been carried out. It shows that stress effects, due to the deformation of the oxide, slows down the chemical oxidation rate and leads to a self-limiting oxide growth. The model predictions are in agreement with the experimental results. [Copyright &y& Elsevier]

Abstract: In this work, we show how to manipulate two-dimensional arrays of Si NCs in thin (⩽10nm) SiO2 layers by ultra-low-energy (⩽1keV) ion implantation and subsequent thermal annealing. The influence of implantation parameters (dose, energy), annealing conditions (temperature, duration, ambient) and oxide thickness on the NCs characteristics (position, size, density) is reported. Particular emphasis is placed upon post-implantation thermal treatments performed in nitrogen-diluted-oxygen ambient that significantly improve the integrity of the oxide and allow for the fabrication of non-volatile memory devices operating at low-gate voltages. Thermal oxidation in N2-diluted-O2 of high-temperature pre-formed silicon NCs has been also examined and modeled using an extended three-dimensional Deal–Grove model. This model reveals that stress effects, due to the deformation of the oxide, slow down the chemical oxidation rate and lead to a self-limiting oxidation of NCs. The model predictions are in agreement with the experimental results. [Copyright &y& Elsevier]

We discuss the distribution of size and aerial density of Ge nanocrystals in a metal-oxide-semiconductor (MOS) memory structure fabricated by molecular beam epitaxy combined with rapid thermal processing; the size and aerial density of Ge nanocrystals are controlled by varying the thickness of the deposited Ge layer and the processing time. Variation of tunnel oxide thickness is demonstrated with the extension of the processing time. The effect of processing time and tunnel oxide thickness on the electrical properties of the MOS structures is investigated by high frequency capacitance-voltage measurements. [ABSTRACT FROM AUTHOR]

An array of cross-point memristive devices has been implemented on the basis of yttria-stabilized zirconia thin film for applications in prototypes of spiking neural networks. The resistive switching phenomena and the plasticity nature of such memristive devices are studied. Reproducible bipolar resistive switching and precise tuning of resistive state are demonstrated and used to implement the plasticity rule according to STDP (spike-timing-dependent plasticity) mechanism. STDP learning is found to be dependent on the memristor's initial resistive state value and discussed in terms of the finite conductance change in studied structures. Obtained results provide the foundation for autonomous neuromorphic circuits with unsupervised learning development. Unlabelled Image • An array of YSZ based cross-point memristors has been implemented for neuromorphic applications. • Resistive switching phenomenon and plasticity nature of YSZ based memristors are studied. • Spike-timing-dependent plasticity is shown to occur in the YSZ based memristors. [ABSTRACT FROM AUTHOR]