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A numerical model describing a magnonic active ring oscillator (MARO) based on a microscopic spin-wave delay line is proposed. The model considers excitation, propagation, and reception of the magnetostatic surface waves in a yttrium iron garnet (YIG) magnetic film with a thickness in the nanometer range. The waves are excited and received with a microscopic coplanar antenna. We employed the model to analyze the influence of the YIG-film thickness and the distance between the antennas on the MARO performance characteristics. We showed that an increase in the delay time inserted by the delay line reduces the phase noise of the MARO and increases the auto-oscillation threshold. In addition, we found a relation between the auto-oscillation threshold, the thickness of the YIG film, and the distance between the antennas. The relation helps design miniature MAROs and suggests a way to reduce the phase noise of the device. The model predicts a phase noise level of −115 dBc/Hz at a 10 kHz offset from an oscillation frequency in the vicinity of 5 GHz for the MARO based on a 100 nm-thick YIG film and 56 μm of distance between the coplanar nano-antennas of the YIG-film based delay line. We believe that this is a clear way forward to microminiaturize the time-delay feedback microwave auto-oscillators. A further reduction in the phase noise down to −125 dBc/Hz at a 10 kHz offset is found in a model of cascaded connection of several microscopic spin-wave delay lines. [ABSTRACT FROM AUTHOR]

We demonstrate an approach to two-dimensional electronic spectroscopy (2DES) that combines the benefits of shot-to-shot detection at high-repetition rates with the simplicity of a broadband white light continuum input and conventional optical elements to generate phase-locked pump pulse pairs. We demonstrate this through mutual synchronization between the laser repetition rate, the acousto-optical deflector, the pump delay stage, and the CCD line camera, which allows for rapid scanning of pump optical delay synchronously with the laser repetition rate, while the delay stage is moved at a constant velocity. The resulting shot-to-shot detection scheme is repetition rate scalable and only limited by the CCD line rate and the maximum stage velocity. Using this approach, we demonstrate the measurement of an averaged 2DES absorptive spectrum in as much as 1.2 s of continuous sample exposure per 2D spectrum. We achieve a signal-to-noise ratio of 6.8 for optical densities down to 0.05 with 11.6 s of averaging at 100 kHz laser repetition rate. Combining rapid scanning of mechanical delay lines with shot-to-shot detection as demonstrated here provides a viable alternative to acousto-optic pulse shaping approaches that is repetition-rate scalable, has comparable throughput and sensitivity, and minimizes sample exposure per 2D spectrum with promising micro-spectroscopy applications. [ABSTRACT FROM AUTHOR]

Microring resonators (MRRs), typically comprising straight and ring waveguides, have played pivotal importance in recent years as far as integrated on-chip systems are concerned. The evanescent coupling in such MRR or solid microdisk resonators is very sensitive to the coupling gap between two waveguides, which affects the resonator's performance. To overcome the stringent requirement of the gap between two waveguides, we propose a coupling-gap-free, on-chip ellipsoid microresonator. The theoretical framework has been deduced to attain the modal properties of such integrated microresonator geometry, which shows an excellent agreement with the finite difference time domain simulations and experimental results. The absence of a coupling region makes the device uniquely compact and robust, with an insertion loss of ∼ 5 dB. The resonator's geometrical dimensions can also be conveniently scaled within certain constraints. The proposed device can be a potential alternative to MRRs and could help in applications such as optical filters, delay lines, on-chip sensing, and many more. [ABSTRACT FROM AUTHOR]

Background Aims Methods Results Conclusions Connecting an infusion line to a closed stopcock results in pressurization of fluid within the syringe infusion pump assembly leading to flow irregularities when opening the stopcock and activating the pump.It was the purpose of this study to assess the extent of pressurization under different conditions and its impact on start‐up fluid delivery.Intraluminal pressures and start‐up fluid delivery at 1 mL/h flow rate were assessed with connection of the infusion line 1 min (delayed connection) or immediately after purging (immediate connection) using two different infusion lines made from polyvinylchloride (PVC) or polyethylene (PE).Delayed connection resulted in an increase of intraluminal pressures from zero to 5.1 [4.5 to 5.7] mmHg with the PVC line and from zero to 47.1 [44.8 to 49.3] mmHg with the PE line (mean difference 42.0 [95% CI 39.3–44.7] mmHg; p < .0001). Immediate connection resulted in an increase of intraluminal pressures from zero to 44.3 [41.8–46.8] mmHg with the PVC line and from zero to 61.3 [57.2–65.4] mmHg with the PE line (mean difference 17.0 [95% CI 11.8–22.2] mmHg; p < .0001). The increase in intraluminal pressures was significantly higher with PE lines for both delayed and immediate connection when compared to the PVC lines (mean difference 29.5 [95% CI 19.3–39.7] mmHg; p < .0001). Related fluid volumes delivered at 10 s and 360 s after starting the pump ranged from −252% to 1321% (10 s) of expected infusion volumes and from 59% to 129% (360 s), respectively.Both, timing of infusion line connection after purging and infusion line characteristics considerably affect intraluminal pressures and start‐up fluid delivery when connecting a new syringe infusion pump assembly to a closed stopcock. Consecutive alterations in drug administration can have considerable hemodynamic consequences when dealing with catecholamine infusions in critically ill patients. [ABSTRACT FROM AUTHOR]

Optical encryption technology attracts considerable attention in the field of information encryption, information storage, and anti‐counterfeiting. However, optical encryption based on conventional on/off mode still faces issues such as low scalability, ease of cracking, and poor storage capacity; multi‐dimensional and high storage capacity information encryption systems are thus needed. Herein, a programmable information encryption circuit system is demonstrated by constructing a delay light‐emitting diode (LED) array using multi‐color phosphorescent carbon nanodots (CNDs) with versatile lifetimes. The CNDs show adjustable luminescence wavelength and lifetime from 192 to 1148 ms. The programmable delay luminescent circuit provides an intricate framework for meticulously integrating an LED array, enabling the creation of intricate patterns or alphanumeric codes. These intricate designs are engineered to serve as a component of an encryption system, which can be deciphered and unveiled under a specific delay time range. This study demonstrates the feasibility and superiority of the system as a new type of information anti‐counterfeiting encryption technology, providing a new concept for exploring the field of integrated circuit anti‐counterfeiting and encryption. [ABSTRACT FROM AUTHOR]

This study comprehensively assesses various recurrent neural networks (RNNs) for decoding the elbow angle from electromyogram (EMG) signals, a crucial aspect in myoelectric interfaces. EMG signals from the shoulder girdle and arm were recorded during goal-directed reaching movements, and linear envelopes were continuously mapped to the elbow angle by three RNN architectures: nonlinear autoregressive exogenous (NARX), Elman, and long-term short memory (LSTM). All three approaches effectively captured the complex dynamics of the multi-input to a single-output regression problem. Regarding within-subject variability, the NARX, Elman, and LSTM demonstrated superior accuracy and robustness compared to dynamic feedforward neural networks like time-delay neural networks. Notably, there was no statistically significant distinction among NARX, Elman, and LSTM estimation performances. Elman and LSTM exhibited an advantage in decoding latent information dependencies through their context layers, leading to improved estimation performance in inter-subject variability analysis, particularly with increased training data volume and variability. Furthermore, the LSTM, with its complex architecture capable of learning long-term temporal dependencies, exhibited the highest performance among the considered RNNs. Consequently, selecting the optimal RNN structure is recommended based on the complexity of the data at hand. The RNN-based decoding model holds potential applications in prosthetics, robotic assistants, and exoskeletons, enabling intention detection and real-time assessment of active rehabilitation progress. [ABSTRACT FROM AUTHOR]

Summary: Despite the performed progressive research work, the interpretation of the negative group delay (NGD) function remains not familiar to non‐specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper deals with the design of a tunable circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using a low‐pass (LP) type NGD circuit is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP‐NGD cell and RC‐circuit is validated with a proof‐of‐concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens‐milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about −0.4 ms was verified thanks to the time‐advanced effect due to the LP‐NGD property. Then, the output signal delay was observed to become positive when the varistor was tuned from 1 kΩ to 3 kΩ. [ABSTRACT FROM AUTHOR]

For ultra-high-speed digital transmission, required by 5G/6G communications, ultra-wideband common-mode rejection (CMR) structures with autonomous phase-balancing capability are proposed. Common-mode noise, caused by phase and amplitude unbalances, is one of the most undesired disturbances affecting modern digital circuits. According to the circuit design guides with a typically used differential line (DL) for high-speed digital transmission, common-mode rejection is achieved using CMR filters, and the unbalanced phase, caused by a length difference between the two signal lines of a DL, is compensated by inserting an additional delay line. However, due to nonlinear phase interactions between the two DLs and unbalanced electromagnetic (EM) interferences, the conventional compensation method is frequency-limited at around 10 GHz. To significantly enhance the common-mode rejection level and extend the phase recovery bandwidth, the proposed CMR structure utilizes a planar balanced line (BL), such as a coplanar stripline (CPS) or a parallel stripline (PSL), along with additional conductor strips arranged laterally near the BL. To demonstrate the performance of the proposed BL-based CMR structures, various types of CMR structures are fabricated, and the measurement results are compared with the 3D EM simulation results. As a result, it is proven that the proposed BL-based CMR structures have the capability to reject the common-mode noise with suppression levels of more than 10 dB and to simultaneously recover the phase balance from near DC to over 40 GHz. [ABSTRACT FROM AUTHOR]

Outbreaks of viral infectious diseases in humans and animals remain one of the global problems of our time. Therefore, one of the most popular areas in applied microbiology is the development of fast and sensitive methods for determining viruses, including those based on biosensor analysis methods. The promise of acoustic sensor systems for detecting viruses is described in this work. The optimal capabilities of electroacoustic sensors in detecting viruses, the possibility of conducting analysis in the presence of interfering factors (viral particles and microflora), and the repeated use of sensors are shown. The promise of using acoustic sensors to determine viruses in microbiology, medicine, and veterinary medicine is demonstrated. [ABSTRACT FROM AUTHOR]

The combination of speed and resolution is a fundamental figure of merit for Fourier transform spectroscopy. Here, we show that, by combining a fast rotational delay line with a strongly modulated quantum cascade laser (QCL), it is possible to perform broadband spectroscopy over a range of 175 cm−1, with a total effective integration time of about 6 s and a resolution of 0.03 cm−1. Remarkably, even though the resolution of the measurement is limited by the source, the interleaving technique can still be applied when the QCL is not in a frequency comb regime, considerably broadening the bandwidth of the instrument. [ABSTRACT FROM AUTHOR]

In this paper we investigate the application of phase-shifting digital holography for the real-time characterization of electromagnetic sources in the THz frequency range. We use an off-the-shelf terahertz detector array composed of 64 × 64 power-sensitive pixels, over an area of 96 mm × 96 mm , to record intensity interferograms cast between the coherent radiation emitted from a reference source and an unknown antenna under test. This approach parallelizes the acquisition process with respect to conventional near-field point scanning methods, reducing the measurement time by orders of magnitude. In our system, the measurement time is limited only by the refresh rate of the detector array and the speed of a delay line stage that is used to phase-shift the reference wave. As a proof-of-principle demonstration, we map the 2D near-field distribution and estimate the far-field radiation pattern emitted by a plano-convex PTFE spherical lens antenna illuminated by a diagonal horn at 290 GHz frequency with ∼ 1 Hz refresh rate. [ABSTRACT FROM AUTHOR]

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process–Voltage–Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field. [ABSTRACT FROM AUTHOR]

This paper describes a study on speaker recognition using the ECAPA-TDNN architecture, which stands for Extended Context-Aware Parallel Aggregations Time-Delay Neural Network. It utilizes X-vectors, a method for extracting speaker features by converting speech into fixed-length vectors, and introduces a squeeze-and-excitation block to model dependencies between channels. In order to better explore temporal relationships in the context of speaker recognition and improve the algorithm's generalization performance in complex acoustic scenarios, this study adds input gates and forget gates to the ECAPA-TDNN architecture, combining them with CIFG (Convolutional LSTM with Input and Forget Gates) modules. These are embedded into a residual structure of multi-layer aggregated features. A sub-center Arcface, an improved loss function based on Arcface, is used for selecting sub-centers for subclass discrimination, retaining advantageous sub-centers to enhance intra-class compactness and strengthen the robustness of the network. Experimental results demonstrate that the improved ECAPA-TDNN-CIFG in this study outperforms the baseline model, yielding more accurate and efficient recognition results. [ABSTRACT FROM AUTHOR]

Model order reduction technique provides an effective way to reduce computational complexity in large-scale circuit simulations. This paper proposes a new model order reduction method for delay circuit systems based on Hermite expansion technique. The presented method consists of three steps i.e., first the delay elements are approximated using the recursive relation of Hermite polynomials, then in the second step, the reduced order is estimated for the delay circuit system using a delay truncation in the Hermite domain and in the third step, a multi-order Arnoldi process is computed for obtaining the projection matrix. In the following, the reduced order delay circuit model is obtained by the projection matrix. Moment matching and passivity properties of the reduced circuit system are also analyzed. Two circuit examples with delay components are performed to verify the effectiveness of the proposed MOR approach. [ABSTRACT FROM AUTHOR]

Summary: This letter presents a design method for dual‐band filtering phase shifters, which is based on E‐type networks. The dual‐band filtering function and different predetermined phase shift values are realized by E‐type networks and two delay lines. The dual‐band bandwidth and frequency ratio can be adjusted. Moreover, the dual‐band phase‐shift bandwidth has been extended. Finally, a dual‐band filtering phase shifter with simple structure and good filtering characteristics is fabricated and measured, which can provide 90 ± 5° and 225 ± 5° phase shifts at 1.75–2.58 GHz and 4.38–5.78 GHz, respectively. All results exhibit a good agreement between the electromagnetic (EM) simulation and measurement results. [ABSTRACT FROM AUTHOR]

As a new planar electrostatic (or, in a better word, quasi-electrostatic) waveguide, the characteristics of electrostatic bulk waves guided by a slab of metallic nanowire-based hyperbolic metamaterials are studied. The dispersion relation of the waves is obtained using the zig-zag ray approach based on the stationary-phase method which is the same as the result obtained from the field analysis. Also, we present a description for the investigation of the group velocity and associated group delay time of electrostatic bulk modes of the system. The analytical results based on the zig-zag ray approach show the group delay is produced partly at the boundaries of the slab and partly inside the slab. The former is not dependent on the order of the mode and can be neglected compared with the latter in the neighborhood of the frequency of resonance where electrostatic wave devices are usually operated. [ABSTRACT FROM AUTHOR]

We provide a comprehensive technical analysis of the data acquisition process with oscillating delay lines for Terahertz-time domain spectroscopy. The utilization of these rapid stages, particularly in high-repetition-rate systems, is known to enable an effective reduction of noise content through averaging. However, caution must be exercised to optimize the data averaging process, with the goal of significantly optimizing the dynamic range (DR) and signal-to-noise ratio (SNR). Here we discuss some pitfalls to avoid and the effect of improper data handling on the dynamic range obtainable. A free and open-source program, called parrot (Processing All Rapidly & Reliably Obtained THz-traces), is provided alongside this publication to overcome the discussed pitfalls and facilitate the acceleration of experimental setups and data analysis, thereby enhancing signal fidelity and reproducibility. [ABSTRACT FROM AUTHOR]

A novel flat negative group delay circuit is proposed. The flatter negative group delay is achieved, and the insertion loss is reduced. The circuit structure consists of a resistor R1 series connected with a capacitor C1 and inductor L1 in parallel, followed by a capacitor C2 and inductor L2 in parallel, and finally connected in series with a capacitor C3 and inductor L3. The analysis design equation is provided. The effects of different component values on circuit flatness and bandwidth are analyzed. According to this design method, a flat negative group delay circuit is designed and fabricated. The simulation and measurement results are basically consistent. It has good flat negative group delay characteristics, with a group delay fluctuation of 3%, a group delay value of −1.02 ns, and an insertion loss of 7 dB. The feasibility of the design method is verified. [ABSTRACT FROM AUTHOR]

Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations. [ABSTRACT FROM AUTHOR]

Aiming to address the timing skew mismatch in the time‐interleaved analog‐to‐digital converter (TIADC) system, this paper presents a timing skew mismatch calibration method based on a back propagation (BP) neural network optimized by an adaptive genetic algorithm (AGA). In this paper, a trained BP neural network is used to detect the timing skew mismatch in the TIADC system, and the variable delay line is used to calibrate it. In this paper, AGA is used to optimize the BP neural network, accelerating its training speed and improving the detection accuracy of timing skew mismatch in the system. The proposed approach boasts superior detection speed and accuracy compared to other methods. In this paper, an 18‐bit 1GS/S 4‐channel TIADC system is simulated and the timing skew mismatch in the system is corrected. Simulation results show that the proposed calibration method has fast detection speed, high detection accuracy, and calibration accuracy. After completing the timing skew mismatch correction, the performance of the TIADC system is dramatically improved. The effective number of bits (ENOB) of the system increases by 9.5 bits, and the spurious‐free dynamic range (SFDR) increases by 59.9 dB. [ABSTRACT FROM AUTHOR]

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150 MHz. The least significant bit (LSB) of the TDC is 21.92 ps. The differential nonlinearity (DNL) is between (−0.976, 1.615) LSB and the integral nonlinearity (INL) is between (−1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783 ps when utilized for measuring various time intervals. [ABSTRACT FROM AUTHOR]

In this study, a high-gain broadband circularly polarized crossed dipole antenna is designed. This antenna utilizes two pairs of cross dipoles and a pair of phase delay lines to form circularly polarized radiation. Open-circuit stubs are symmetrically loaded on the four arms of these dipole pairs to introduce new circularly polarized resonating frequencies. Additionally, a symmetrically positioned rectangular ring patch is introduced directly beneath the cross dipoles to generate the third circularly polarized resonating frequency, thereby enhancing the axial ratio bandwidth of the antenna symmetrically. Furthermore, metal posts are symmetrically loaded at the four right angles of the rectangular ring patch to augment the antenna gain, maintaining the overall symmetrical balance crucial for optimal circularly polarized radiation performance. This symmetric design ensures that the antenna achieves a 3dB axial ratio bandwidth of 29.2% (1.9–2.55 GHz) and sustains a gain of 7.5 dB within the passband, showcasing excellent circularly polarized radiation attributes. [ABSTRACT FROM AUTHOR]

This Letter demonstrates the use of long-lifetime NO fluorescence for molecular tagging velocimetry (MTV) with (1 + 1) resonant-enhanced multiphoton ionization (REMPI) scheme, utilizing a single laser beam in a detonation-driven hypersonic shock tunnel. The Q1 branch of the NO A ← X (0, 0) transition was excited using radiation near 226.256 nm. It was determined that (1 + 1) REMPI of NO generates long lifetime fluorescence, and this observation is consistent with the findings reported by Jiang et al. [Opt. Lett. 49, 1297–1300 (2024)] and Leonov et al. [Opt. Lett. 49, 426–429 (2024)]. Single-shot tagged lines at microsecond delay times were obtained in a Ma6.9 hypersonic freestream flow using a long focal length lens. The measured average velocity of 3477 m/s agrees well with the simulation result. [ABSTRACT FROM AUTHOR]

A novel multi‐band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An n‐order bandpass negative group delay circuit was analyzed and presented, and taking a three‐frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi‐bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB. [ABSTRACT FROM AUTHOR]

In image processing, the noticeable variations of the image can be found using the edge detection process. This edge detection process facilitates to identify placement and edges of an object. The Sobel edge detection process is preferred since it is simple and more noise immune. Sobel edge detection calculates gradients of a pixel in horizontal and vertical directions concerning neighboring pixels. The gradients absolute quantities are computed, added, and matched to a threshold for finding whether the pixel is an edge pixel or not. In this paper, the Sobel edge detection system VLSI architecture is designed which consumes less power by using the arithmetic blocks like Brent Kung adders. The source image of different resolutions is taken to perform Sobel edge detection and implemented using various FPGA devices by analyzing power dissipation, delay and device utilization summary. Then, simulation, synthesis processes are performed and finally, power analysis is performed using XPower Analyzer of Xilinx ISE software. [ABSTRACT FROM AUTHOR]

The most promising emerging technology that can reduce the power, area and delay in digital circuits is Quantum-dot Cellular Automata (QCA) technology. The Serial Input-Serial Output (SISO) Shift Register (SR) is a basic component in digital circuits. The SISO SR can be designed using two methods in the QCA technology, directly mapping circuits from the CMOS technology and using the inherent capability of the QCA technology. This paper presents and evaluates the new n -bit QCA SISO SR that not only uses the inherent capability of QCA technology but also has a regular architecture. The proposed n -bit SISO SR is developed based on the building block, which is designed in this paper. In addition, the developed QCA SISO SR has coplanar architecture and it has the ability to correct or change data. The proposed n -bit SISO SR is evaluated for 3, 4 and 5 bits using QCADesigner- E. The results demonstrate that the designed circuits for 3-, 4- and 5-bit QCA SISO SRs require 68 (0.06 μ m 2) , 92 (0.08 μ m 2) and 116 (0.09 μ m 2) cells (area), respectively. The comparison demonstrates that the developed QCA SISO SRs have advantages in comparison to other QCA SISO SR circuits. An efficient architecture has been presented to design novel architecture for n-bit QCA SISO SRs. The designed architecture has coplanar architecture. It not only has regular architecture, but also uses hybrid of inherent capability of the QCA and CMOS technology. The comparison of the obtained results demonstrates that the designed SRs have advantages in comparison with other SRs in the QCA technology. [ABSTRACT FROM AUTHOR]

The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC's post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a multiphase digital control called digital integration constant on‐time (DICOT) control is proposed, which applies the concept of signal accumulation, solves the drawbacks of ripple‐based digital COT control that the switching frequency and transient performance are affected by the A/D sample delay and sampling noise. Besides, the multiphase interleaving approach of the proposed DICOT control is well‐suitable for digital control and no higher calculation frequency is required compared to single‐phase. In the aspect of the current balance, almost all existing researches work on analog COT current balance scheme and few works are investigating the resolution improvement of digital COT current balance. In this paper, the current balance model of multiphase COT control is derived and can be applied in the Buck system with an arbitrary number of phases, the delay‐line‐based high‐resolution COT current balance scheme is proposed to enhance the control resolution. Finally, the two‐phase DICOT control is tested on the multiphase Buck system, the transient performance is tested of 100 A load step with the slew rate of 1000 A/μs, and the voltage undershoot and overshoot are 20 and 36 mV, respectively. The current balance is tested and the errors are 0.01% and 0.11% at the light and heavy loads, respectively. [ABSTRACT FROM AUTHOR]

The design of arrays capable of receiving wideband signals differs from arrays that can only receive narrowband signals. These arrays must be able to receive signals with an instant bandwidth of several GHz across the entire operating frequency, such as High‐Resolution Radars or Terahertz in 6G communication systems. In these arrays, using a time delay line structure leads to an increase in beamformer coefficients, resulting in high computational complexity. This poses a challenge for beamforming in wideband systems. Additionally, classic Wideband beamformers face other factors, such as poor performance in the presence of input direction of arrival error, array calibration error, and requiring too many snapshots to reach the steady state of the beamformer. Therefore, the robustness of wideband adaptive beamforming using deep unfolding model‐based technique is focused on, which has not been discussed before. The advent of deep unfolding, an innovative technique, amalgamates iterative optimization approaches with elements of neural networks. The aim is to deftly maneuver through various tasks across disciplines such as machine learning, signal and image processing, and telecommunication systems. Also, the network training method is done to become more robust against the mentioned factors. In the proposed structure, the constraints of the previous methods have been evaluated. It is observed to have better performance compared to other classic algorithms. Also, with the investigations of the proposed method with other conventional deep learning methods, it was observed that in some cases the proposed structure performance is equal to the conventional deep learning method and sometimes better. [ABSTRACT FROM AUTHOR]

We numerically propose a vertically coupled ring resonator with a high extinction ratio and tunable group delay based on Silicon (Si)–Indium Tin Oxide (ITO) heterojunction. The vertically coupled ring and bus waveguide configuration offers several advantages including, improved coupling efficiency, and reduced propagation losses, which allows for efficient coupling between the Si-bus waveguide and the Si–ITO ring, leading to stronger light–matter interaction and enhanced light transmission. The Si–ITO heterojunction within the ring resonator enables electrically varying carrier concentration of ITO, thereby reaching the epsilon-near-zero (ENZ) region. The achievement of the ENZ region leads to enhanced optical absorption and improved device performance. The proposed device exhibits a high extinction ratio of 20.5 dB. Moreover, the voltage-dependent group delay of the device exhibited a significant variation of 29 psec when the applied voltage is varied within the range of − 4 V to 4 V. The voltage-tunable vertically coupled Si–ITO heterojunction-based ring modulator offers a promising platform for integrated photonics, with potential applications in optical communication, signal processing, and sensing. [ABSTRACT FROM AUTHOR]

This paper presents a compact wideband circularly polarized cross-dipole antenna with a low-pass filter response. It consists of two pairs of folded cross-dipole arms printed separately on both sides of the top substrate, and the two dipole arms on the same surface are connected by an annular phase-shifting delay line to generate circular polarization. A bent metal square ring and four small metal square rings around the cross-dipoles are employed to introduce new resonant frequencies, effectively extending the impedance and axial-ratio bandwidth. Four square patches printed on the middle substrate are connected to the ground plane by the vertical metal plates in order to reduce the antenna height. Thus, a compact wideband circularly polarized antenna is realized. In addition, a transmission zero can be introduced at the upper frequency stopband by the bent metal square rings, without using extra filter circuits. For verification, the proposed model is implemented and tested. The overall size of the model is 90 mm × 90 mm × 33 mm ( 0.37 λ 0 × 0.37 λ 0 × 0.14 λ 0 ; λ 0 denotes the center operating frequency). The measured impedance bandwidth and 3 dB axial-ratio (AR) bandwidth are 53.3% and 41%, respectively. An upper-band radiation suppression level greater than 15 dB is realized, indicating a good low-pass filter response. [ABSTRACT FROM AUTHOR]

The structure of arrays capable of receiving wideband signals differs from arrays which can only receive narrowband signals. These arrays should be capable of receiving several GHz instant bandwidth signals over the entire operating frequency, like High Resolution Radars or Terahertz in 6G communication systems. In these arrays, the number of beamformer coefficients increase due to using a time delay line structure, hence leading to a high computational complexity. This is one of the challenges of beamforming in wideband systems. Additionally, there are other factors in classic Wideband beamformers. These factors include poor performance against input DOA (direction of arrival) error, array calibration error, and too many snapshots to reach the steady state of the beamformer. Therefore, this paper focuses on the robustness of beamforming using deep learning technique, which has not been discussed before. The basis of network design is convolutional layers. Two different proposed approaches have been proposed to obtain optimal structure. In the first approach, appropriate values of hyperparameters are estimated, whereas the network model is selected in the second approach. Also, the network training method is done to become more robust against the mentioned factors. In the proposed structures, the constraints of the previous methods have been evaluated. The proposed structure is shown to have a superior performance when compared with other existing algorithms. In addition, the matrix of signal samples is replaced with the covariance matrix at the network's input, so the calculation time is significantly improved compared to the previous methods. [ABSTRACT FROM AUTHOR]

This paper investigates the Hopf-like bifurcation of a fractional tumor-lymphatic model with two time delays. The two time delays are considered as branching parameters, and we analyze their influences on the dynamic properties of the model. Through an examination of the root distribution of the characteristic equation, we derive the properties of the positive steady state and the conditions for the occurrence of Hopf-like bifurcation near the positive equilibrium point. Numerical simulations are demonstrated to support our theoretical results. [ABSTRACT FROM AUTHOR]

This letter proposes a millimeter‐wave dual‐polarized (DP) end‐fire frequency scanning antenna utilizing low temperature co‐fired ceramic (LTCC) technology. The antenna features DP radiating elements, each comprising a quasi‐Yagi antenna for horizontal polarization (H‐pol) and a pyramidal horn antenna for vertical polarization (V‐pol). These elements are excited via a mode‐composited transmission line (MCTL), integrating substrate integrated coaxial line (TEM mode) with substrate integrated waveguide (TE10 mode). To mitigate phase imbalances between polarizations during beam scanning, a delay line is embedded in each quasi‐Yagi element, ensuring consistent scanning ranges for the two polarizations. Furthermore, the implementation of amplitude weighting in the feeding networks contributes to the enhancement of antenna efficiency. A 1 × 8‐element prototype was fabricated and its performance is assessed. The results show closely matched beam scanning ranges for the two polarizations (±28° for H‐pol and −30° to +34° for V‐pol) across the 26–29 GHz frequency band, with a measured maximum peak gain exceeding 9.2 dBi for both polarizations. The proposed design emerges as a promising candidate for compact mmW frequency scanning front‐end antenna systems. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

In this paper, we design the first semiquantum private comparison (SQPC) protocol which is realized via cavity quantum electrodynamics (QED) by making use of the evolution law of atom. With the help of a semi-honest third party (TP), the proposed protocol can compare the equality of private inputs from two semiquantum parties who only have limited quantum capabilities. The proposed protocol uses product states as initial quantum resource and employs none of unitary operations, quantum entanglement swapping operation or delay lines. Security proof turns out that it can defeat both the external attack and the internal attack. [ABSTRACT FROM AUTHOR]

Power efficiency and enhancing the speed are two major challenges of traditional D-Flip-Flops (D-FF) for designing energy-efficient IOT (internet of thing) devices. Therefore, the main objective of this research article is to design low power high speed D-FF circuits using emerging nanoscale devices. Hence, the first time, in this paper, a pulse-triggered Junctionless D-Flip-Flop (JLFET D-FF) circuit is presented using 15 nm technology, targeting both power budget and high performance concerns. Here, the D-FF circuit uses a signal feedthrough approach to minimize transition duration when output switches from 0 to 1, which requires only a single JLFET structure. Further, to minimize the delay time for the 1 to 0 transition, the discharging path is optimized by employing only two JLFETs. The novel JLFET D-FF circuit is simulated in the Cadence virtuoso simulator using the Verilog-A model. The simulated results have shown that the average power consumption and delay of the proposed circuit are significantly improved as compared to the earlier reported work. The average power consumption in JLFET D-FF for 25% data switching activity is improved by approximately 56% and 64% than ULPFF and SFT-FF, respectively. Further, the power delay performance (PDP) of JLFET D-FF is improved by 96% and 97% at the same data switching activity as compared to ULPFF and SFT-FF, respectively. The performance of the novel D-FF circuit is measured by considering D to Q delay as key parameter which is improved by 77% and 77.5% than ULPFF and SFT-FF, respectively. The simulation results of this work can give insights into the in-circuit behavior of modern semiconductor devices. [ABSTRACT FROM AUTHOR]

This paper describes an efficient method of designing and implementing in FPGA devices complex tapped delay lines (CTDL) with pico and sub-picosecond resolution. Achieving a higher resolution and better linearity is possible by appropriate selection of single time coding tapped delay lines (TDL) involved in creation of CDTL. The proposed TDL selection algorithm significantly optimizes the size of the device's logical resources required to implement CDTL with assumed parameters and provides a proper selection scenario. Ultimately, the presented solution allows to create CTDLs with different user-defined configurations based on a fixed set of available logical resources. Therefore, it is particularly recommended for prototyping in smaller FPGA devices. In this work, we investigate how the order of line selection influences the increase of the multiple time coding lines resolution. Furthermore, we determine the relation between the equivalent resolution value and the number of TDLs involved. Obtained results allow to estimate the upper limit of resolution that can be achieved using a given technology. In addition, the ranges of resolutions achievable with a fixed number of lines is also examined. The presented research results have been performed on a Kintex UltraScale FPGA chip, manufactured by Xilinx in the 20-nm CMOS process. [ABSTRACT FROM AUTHOR]

Ice accumulation on infrastructure poses severe safety risks and economic losses, necessitating effective detection and monitoring solutions. This study introduces a novel approach employing surface acoustic wave (SAW) sensors, known for their small size, wireless operation, energy self-sufficiency, and retrofit capability. Utilizing a SAW dual-mode delay line device on a 64°-rotated Y-cut lithium niobate substrate, we demonstrate a solution for combined ice detection and temperature measurement. In addition to the shear-horizontal polarized leaky SAW, our findings reveal an electrically excitable Rayleigh-type wave in the X+90° direction on the same cut. Experimental results in a temperature chamber confirm capability for reliable differentiation between liquid water and ice loading and simultaneous temperature measurements. This research presents a promising advancement in addressing safety concerns and economic losses associated with ice accretion. [ABSTRACT FROM AUTHOR]

In this paper, the event-triggered-based cluster-delay consensus control problem is investigated for leader-following nonlinear multi-agent systems (MASs). In control design, both state triggering in the agents' network and constant time-delay in the leaders' communication network are considered. Under the framework of Lyapunov function stability theory, the Lipschitz condition is used to overcome the influence caused by time-delay. In order to further effectively utilize data transmission resources, and reduce the communication load of the topology network between each agent, an event-triggered mechanism is established. Subsequently, a robust cluster consensus control strategy is proposed based on event-triggered mechanism, which can ensure all signals of the controlled system are bounded, and the tracking errors converge to zero. In addition, it can also effectively avoid the Zeno behavior. Finally, the effectiveness of the presented control method and theory is verified by a simulation example. [ABSTRACT FROM AUTHOR]

Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software's were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker's perspective instead of mitigation perspective. [ABSTRACT FROM AUTHOR]

In this study, issues regarding testing and tuning electronic equipment using pulse generators with precisely maintained timing parameters of output signals synchronized with the device under testing are presented. The dependence of the error in the timing parameters of the output pulses of the generators on the selected synchronization method is described, while the time interval required for synchronization can limit the maximum frequency of the testing signals. It is demonstrated that the main source of errors in the formation of time intervals during external triggering (operating mode with external synchronization) of measuring pulse generators of the G5 group is the variation in the position of the reference pulses of the clock-signal generator relative to the external triggering pulses. An analytical review of synchronization methods based on the sampling of time intervals by a multitap delay line (MDL) when a pulse signal propagates through it is presented. The method of instantaneous synchronization of output pulses is studied, which uses sampling of the period of the reference pulses of the clock-signal generator with a MDL and fixing by triggering the position of the front of the external trigger pulse within the period of the reference frequency. Triggers control a multiplexer that connects the output of a MDL to the output of the device, at which the front of the next reference pulse of the clock-signal generator lags by a minimum time from the front of the external trigger pulse. A device is presented that can be used to implement this method. Computer simulations to illustrate the details of the device functioning are performed. Jitter is estimated on a prototype device using integrated five-tap delay lines at a total delay of 20 ns. The proposed method can be applied in measuring pulse generators and other pulse technologies. Overall, this study is useful to developers of devices for generating synchronization signals in computing and measuring systems operating in asynchronous mode. [ABSTRACT FROM AUTHOR]

The effective detection of isopropyl methylfluorophosphonate (GB, sarin), a type of organophosphine poisoning agent, is an urgent issue to address to maintain public safety. In this research, a gas-sensitive film material, poly (4-hydroxy-4,4-bis trifluoromethyl)-butyl-1-enyl)-siloxane (SXFA), with a structure of hexafluoroisopropyl (HFIP) functional group was synthesized by using methyl vinylpropyl dichlorosilane and hexafluoroacetone trihydrate as initial materials. The synthesis process products were characterized using FTIR. SXFA was prepared on a 200 MHz shear surface wave delay line using the spin-coating method for GB detection. A detection limit of <0.1 mg/m3 was achieved through conditional experiments. Meanwhile, we also obtained a maximum response of 2.168 mV at a 0.1 mg/m3 concentration, indicating the much lower detection limit of the SAW-SXFA sensor. Additionally, a maximum response standard deviation of 0.11 mV with a coefficient of variation of 0.01 and a maximum recovery standard deviation of 0.22 mV with a coefficient of variation of 0.02 were also obtained through five repeated experiments. The results show that the SAW-SXFA sensor has strong selectivity and reproducibility, good selectivity, positive detection ability, high sensitivity, and fast alarm performance for sarin detection. [ABSTRACT FROM AUTHOR]

The success of next-generation Internet of Things (IoT) applications could be boosted with state-of-the-art communication technologies, including the operation of millimeter-wave (mmWave) bands and the implementation of three-dimensional (3D) networks. With some access points (APs) mounted on unmanned aerial vehicles (UAVs), the probability of line-of-sight (LoS) connectivity to IoT nodes could be augmented to address the high path loss at mmWave bands. Nevertheless, system optimization is essential to maintaining reliable communication in 3D IoT networks, particularly in dense urban areas with elevated buildings. This research adopts the implementation of a geometry-based stochastic channel model. The model customizes the standard clustered delay line (CDL) channel profile based on the environmental geometry of the site to obtain realistic performance and optimize system design. Simulation validation is conducted based on the actual maps of highly dense urban areas to demonstrate that the proposed approach is comprehensive. The results reveal that the use of standard channel models in the analysis introduces errors in the channel quality indicator (CQI) that can exceed 50% due to the effect of the environmental geometry on the channel profile. The results also quantify accuracy improvements in the wireless channel and network performance in terms of the CQI and downlink (DL) throughput. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

The brain is known to be plastic, i.e., capable of changing and reorganizing as it develops and accumulates experience. Recently, a novel form of brain plasticity was described which is activity-dependent myelination of nerve fibers. Since the speed of propagation of action potentials along axons depends significantly on their degree of myelination, this process leads to adaptive change of axonal delays depending on the neural activity. To understand the possible influence of the adaptive delays on the behavior of neural networks, we consider a simple setup, a neuronal oscillator with delayed feedback. We show that introducing the delay plasticity into this circuit can lead to the occurrence of slow oscillations which are impossible with a constant delay. [ABSTRACT FROM AUTHOR]

High frequency (HF) transmitter implemented with the multioctave broadband power amplifier (PA) is always faced with the problem of interfering harmonics because of the nonlinearity of the PA. With the harmonic‐cancelation digital predistortion (HC‐DPD) scheme, the harmonics at lower frequencies can be canceled by the injected components and the harmonics at higher frequencies can be filtered out using a low‐pass filter (LPF). However, the HC‐DPD scheme brings the problem of unwanted spurs while lowering the requirements for sampling rate. In this article, a time‐delay neural network (TDNN) model is used to replace the conventional memory polynomial (MP) model in the forward modeling. Theoretical derivation and simulation results validate the effectiveness of the TDNN model in harmonic cancelation and spur suppression. Further, a frequency‐agile neural network (FANN) model is proposed based on the TDNN model. By adding the carrier frequency to the inputs of the network, the trained model can apply to all the trained carrier frequencies and is more friendly to the frequency‐hopping scenarios. Experiments were carried out on a 2–30 MHz HF transmitter testbench. Measurement results show that the harmonic‐to‐fundamental power ratio, the adjacent channel power ratio (ACPR), and the error vector magnitude (EVM) performances were all improved by more than 20 dB. Compared with the MP model, the unwanted spurs can be suppressed by up to 22 dB. In addition, the number of total model coefficients of the proposed FANN model is only 22% of that of the TDNN model under the frequency‐hopping scenario. [ABSTRACT FROM AUTHOR]

Summary: In this work, the analysis of negative group delay circuits in fractional domain has been conducted. The low pass and the high pass negative group delay circuits constructed based on passive network have been chosen as our candidate circuits. For performing the analysis in fractional domain, the novel Caputo–Fabrizio derivative‐based fractional impedance have been introduced to both circuits. The crucial parameters, the necessary conditions, and the existence conditions of both candidate negative group delay circuits have been formulated. The simulations have been conducted based on the formulated results where the comparisons with the conventional prototypes have been made. The verifications by the proof‐of‐concept circuits have also been performed. In addition, the effects of variation in the order of fractional impedances have been investigated. In summary, it has been found that considering these negative group delay circuits in the fractional domain, which effectively taking unavoidable nonidealities that cannot be modeled in conventional domain into account, significantly alters their characteristics especially the low pass circuit. However they can retain their low pass and high pass negative group delay functions. [ABSTRACT FROM AUTHOR]

The Von Neumann architecture has been the foundation of modern computing systems. Still, its limitations in processing large amounts of data and parallel processing have become more apparent as computing requirements increase. Neuromorphic computing, inspired by the architecture of the human brain, has emerged as a promising solution for developing next-generation computing and memory devices with unprecedented computational power and significantly lower energy consumption. In particular, the development of optoelectronic artificial synaptic devices has made significant progress toward emulating the functionality of biological synapses in the brain. Among them, the potential to mimic the function of the biological eye also paves the way for advancements in robot vision and artificial intelligence. This review focuses on the emerging field of optoelectronic artificial synapses and memristors based on low-dimensional nanomaterials. The unique photoelectric properties of these materials make them ideal for use in neuromorphic and optoelectronic storage devices, with advantages including high carrier mobility, size-tunable optical properties, and low resistor–capacitor circuit delay. The working mechanisms, device structure designs, and applications of these devices are also summarized to achieve truly sense-storage-computer integrated optoelectronic artificial synapses. [ABSTRACT FROM AUTHOR]