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The generalized CMRR analysis of the CMOS current feedback instrumentation amplifier (CFIA), in drain and source feedback configurations (termed DCFIA and SCFIA), is developed by focusing on the input stage. The random CMRR for processes (CMRRP) of the CFIAs are derived as a function of the transistor dimensions, small-signal and operating parameters, as well as the process-dependent mismatch factors, to gain insights into the statistical CMRR characteristics, which enables better design optimization. Simplification of the analysis based on practical constraints yields closed-form CMRRP equations that reveal different design considerations for the two CFIA configurations. For example, while the DCFIA relies on the matching of the input transistors, the matching of the drain load transistors is critical for CMRRP enhancement of the SCFIA (this criterion differs from established design practice). The analysis also reveals that unlike the SCFIA, the DCFIA features a direct tradeoff between noise and CMRRP. The integrity of the analysis is validated by comparison with simulations of various published CFIAs designed in a 0.35-\mum CMOS process. [ABSTRACT FROM AUTHOR]

In this paper, a study of bulk degeneration in a differential pair to enhance its linear range is initially conducted. A nanopower operational transconductance amplifier (OTA) is then proposed combining both source and bulk degeneration to achieve an increased linear range above 1 V with a power supply ranging from 1.9 V to 5.5 V. The circuit was fabricated in a 0.6 µm technology and measured. This linearity improvement is achieved with a negligible increase in power consumption, noise, and input referred offset. Finally a circuit implementing the full signal conditioning of a piezoelectric accelerometer for adaptive pacemakers is presented, as an application example of the proposed OTA. The circuit consumes only 500 nA, and it can discriminate signals of 15 µV, because of the low input referred offset < 5 mV of the source-bulk linearized OTA. [ABSTRACT FROM PUBLISHER]

A tunable CMOS Gm-C channel-select low-pass filter is presented. Class AB operation overcomes the dynamic range versus static power tradeoff of conventional channel-select filter topologies. Programmable transconductors are designed using quasi-floating gate transistors, which provide class AB operation without requiring extra supply voltage or power requirements and keeping accurately set quiescent currents. The filter can be applied to channel selection in highly integrated, low power zero-IF wireless receivers. For example, its frequency tuning range and linearity makes it suitable for a dual-mode Bluetooth/ZigBee zero-IF receiver. Measurement results for a test chip prototype in a 0.5 \mum standard CMOS process are presented, showing a THD < -55 dB for an input of 1.2 Vpp, which corresponds to peak currents 300% larger than the bias current. [ABSTRACT FROM PUBLISHER]

Floating-gate and quasi-floating gate MOS transistors can be efficiently employed to design CMOS transconductors. These transistors allow achievement of relevant features in a compact and simple way, such as rail-to-rail input range, continuous transconductance tuning, and class AB operation. This paper illustrates how these techniques can be applied by employing them in the design of two transconductors, which have been fabricated in a 0.5 \mu \m CMOS process. Measurement results confirm the advantages of the proposed approach. [ABSTRACT FROM PUBLISHER]

A comprehensive analysis of tunable transconductor topologies based on passive resistors is presented. Based on this analysis, a new CMOS transconductor is designed, which features high linearity, simplicity, and robustness against geometric and parametric mismatches. A novel tuning technique using just a MOS transistor in the triode region allows the adjustment of the transconductance in a wide range without affecting the voltage-to-current conversion core. Measurement results of the transconductor fabricated in a 0.5-μm CMOS technology confirm the high linearity predicted. As an application, a third-order Gm-C tunable low-pass filter fabricated in the same technology is presented. The measured third-order intermodulation distortion of the filter for a single 5-V supply and a 2-Vpp two-tone input signal centered at 10 MHz is -78 dB. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current [ABSTRACT FROM PUBLISHER]

A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8- μm CMOS process. Experimental results show a frequency timing range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption. [ABSTRACT FROM AUTHOR]