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This paper introduces a concurrent computing technique for the acceleration of digital stochastic measurement simulations. The digital stochastic measurement presents an advanced methodology based on the specific parallel hardware structure, utilized for an orthogonal transformation calculus/decomposition. Methodology is analyzed in detail, starting from the very basic idea, toward recent references, covering main research directions and trends. An oversampling nature of the evaluated digital stochastic measurement, along with demanding arithmetic requirements, implies exhausting simulation complexity. As a test case, several typical power grid signals were harmonically analyzed through a discrete Fourier transformation based on the proposed methodology. A harmonic decomposition was simulated with several levels of computing concurrency. Through all the simulated scenarios main success criterion was model accuracy, while the parameter used for selection of the optimal simulation computing technique was the overall calculus speed. Final results exposed thread pool computing technique as an optimal simulation platform. [ABSTRACT FROM AUTHOR]

The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking. [ABSTRACT FROM AUTHOR]

In this paper, a comprehensive power line test bed for the automatic meter reading (AMR) system is developed. Such a test bed builds a 220V power line environment in which the intensity and types of simulated noise can be configured very flexibly. It facilitates the fast analysis of the running condition of AMR system and power line carrier communication (PLCC). In particular, a new simulation technique, which is dedicated to modeling the power line cyclostationary noise, is proposed in this paper through analyzing many unique power line noise characteristics. It is further integrated with a noise simulator which handles the controllable noise replayer and time-varying loads to make the whole simulation system more salient. The experimental results demonstrate that the proposed simulator is highly effective. Our simulator can handle the communication tests with a wide frequency range, from 10kHz to 500kHz with high accuracy. [ABSTRACT FROM AUTHOR]

Wireless sensor networks (WSNs) are an attractive choice for many applications where sensors are densely and efficiently deployed in an area of interest. For example, in surveillance applications, where deterministic placement is not applicable, the sensors have to be randomly deployed entirely or partially in an area. Whether random or deterministic, the strategy of deploying the sensors has a large impact on the performance of WSNs. In this paper, we propose a systematic methodology for sensors placement based on several random distributions. The quality of deployment is evaluated using a set of proposed measures, the significance of which highly depends on the WSN application. The impact of these deployment strategies on the network performance is thoroughly studied. Moreover, we propose a new hybrid deployment strategy that aims to achieve the best performance based on the suggested deployment quality measures. Both the placement strategies with the deployment quality measures are evaluated using extensive simulations. The results show that the proposed hybrid strategy outperformed other strategies including uniform, random, Gaussian, and exponential distributions. In addition, the paper identifies the family of applications where each of the quality measures is highly critical. [ABSTRACT FROM AUTHOR]

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5-3.3V, the output voltage after 25s with load current of 100mA, is determined with ripple less than 1.8mV. In sudden changes, the load current at the range 0-100mA, and output voltages after a maximum 15.5s with an input voltage of 3.3V have the highest ripple in output voltage of 4mV. [ABSTRACT FROM AUTHOR]

This paper presents the design of novel autonomous and non-autonomous inductorless chaotic circuit using lambda diode. The autonomous chaotic circuit is implemented using Chua's circuit, where the piece-wise linear element of Chua's circuit called Chua's diode is replaced by lambda diode. The lambda diode used as a nonlinear resistor in Chua's circuit comprises of BJT, FET and resistors. The non-autonomous chaotic circuit is studied by replacing the piece-wise linear element of Murali-Lakshmana-Chua (MLC) circuit by lambda diode. The reason for employing lambda diode is that it has a wide range of negative resistance characteristics, which enable the circuit to operate at higher frequency ranges. The resulting chaotic oscillator can easily be made to operate at both low and high frequencies. The chaotic behavior of the circuit is established through Multisim simulations in the time and frequency domains. Both theoretical analysis and electronic circuit experiments are presented. The circuit's chaotic characteristics are further confirmed by means of Poincare plot and the Bifurcation diagram. The observed route to chaos is period-adding. [ABSTRACT FROM AUTHOR]

In this paper, a frequency-tunable dynamic pulse integrating circuit for infrared receivers is presented. The proposed circuits possess many advantages, such as high sensitivity, high immunity against disturbances, simple structure, and so on. This integrator not only defines a minimum time for the burst length and a minimum time between the bursts, but also achieves the same minimum number of pulses in different frequencies. The frequency-tunable dynamic pulse integrator is a combined structure of the center frequency modulation and a new type of pulse integrator. The center frequency modulation is implemented by using zener zap anti-fuse trim and a second-order band-pass filter (BPF) with bipolar operational transconductance amplifier (OTA) cell. The integrator also describes the characteristics of variable-error tolerance to prevent the output envelope error due to the lack of individual pulses. The results of simulation are shown that the center frequency is available from 33 to 40 kHz and 56 kHz in typical application by Cadence respectively. Moreover, the minimum burst length is 10 pulses and minimum bursts gap time is 14 pulses in typical application. [ABSTRACT FROM AUTHOR]

According to the terminal relations of the DO-OTA, eight nullor-mirror models for the DO-OTA are presented in this paper, Moreover, the NAME method for two different classes of T-T filters is considered. The class I filters, employing three SISO-OTAs, have 16 different forms, and the class II filters, employing one SISO-OTA and one DISO-OTA or one SIDO-OTA, have eight different forms. Due to use of canonic number of components, the circuits are easy to be integrated and their parameters can be tuned electronically through tuning bias currents of the OTAs. The MULTISIM simulation results have been included to verify the workability of the derived circuit. [ABSTRACT FROM AUTHOR]

With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results. [ABSTRACT FROM AUTHOR]

A novel substructure (dominant eigenvalue) preserving genetic algorithm approach for model order reduction (MOR) of multi-time-scale systems is presented in this paper. The new technique is formulated based on genetic algorithms (GAs), sub-optimization and estimation. The GA predicts the elements of an upper triangular matrix form of the system state matrix A, defined in state space representation along with the elements of B, C, and D matrices. The GA procedure is based on maximizing the fitness function corresponding to the reciprocal response deviation between the full order model and the reduced order model. The proposed GA model order reduction method is compared to well-known reduction techniques such as the Balanced Schur Decomposition (BSD), proper orthogonal decomposition (POD), and state elimination through balanced realization. Simulation results validate the robustness of the new technique for MOR with eigenvalue preservation. [ABSTRACT FROM AUTHOR]

A fully cascadable (i.e., low/high input impedance for current/voltage input signals and high/low output impedance for current/voltage output signals) mixed-mode (input and output signals can be voltage or current) universal filter biquad by using three differential difference current conveyors (DDCCs), three grounded resistors, and two grounded capacitors is presented in this paper. The proposed biquad can realize the inverting, non-inverting, and differential types universal filtering responses (lowpass, highpass, bandpass, notch, and allpass) from the voltage and current output terminals without changing the filter topology. The proposed circuit is suitable for cascading in all the four possible modes (i.e., voltage, current, transresistance, and transconductance modes). Moreover, the proposed mixed-mode biquad still enjoys (i) using only grounded passive components, (ii) no need of extra inverting and non-inverting amplifiers for special input signals, and (iii) low active and passive sensitivities. This paper also shows how analytical synthesis can be used to produce the proposed mixed-mode filter circuit. H-Spice simulation results confirm the theory. [ABSTRACT FROM AUTHOR]

Tailored for the best effort service, the present paper deals with dynamic allocation of subcarriers, rate and power resources based on channel state information (CSI) for multiuser MIMO-OFDM systems with trellis code modulation (TCM). Users rely on adaptive modulation and power modes that they select in accordance with the finite-rate feedback (FRF) they receive from the base station (BS). The BS uses CSI to maximize a generic concave utility of average rates while adhering to power constraints imposed on every user. We utilize a stochastic approximation primal-dual algorithm for on-line scheduling and resource allocation. The resultant optimum resource allocation depends on the current channel realization and optimally calculates dual prices. The simulation results show that the system throughput of proposed algorithm is not only good but also can effectively reduce the feedback overhead and the adoption of TCM can improve the system throughput greatly comparing to uncoded system. [ABSTRACT FROM AUTHOR]

This paper presents a simplified analysis of a generalized cycloconverter and suggests a new method for the estimation of the cycloconverter period as a function of the control mode. The paper presents generalized theoretical results supported by computer simulations and demonstrated by examples. [ABSTRACT FROM AUTHOR]

A class of singular nonlinear systems with set-valued mappings are studied in this paper. Criteria are given based on the Lyapunov function to check the absolute stability of the systems, then the results are extended to the time delay systems and the time delay systems with uncertainty. Three examples are simulated to show the e®ectiveness of the proposed stability conditions. [ABSTRACT FROM AUTHOR]

The multilevel inverter (MLI) has ascertained its gravity in high-power applications for the past three decades through perennial topological modifications from the pristine structure and development of apposite modulation strategies. The benefits, including subtle switch voltage stress, reduced output voltage total harmonic distortion (THD), tolerable electromagnetic compatibility (EMC), minimal switching losses and d v / d t stress, have prepared it as a very promising candidate in high-power drives and electric utility applications. Meanwhile, MLI has few drawbacks such as higher number of switches with associated peripherals (gate driver circuits, protection circuits and heat sinks) which makes the overall system complex, bulky and costly. There have been many attempts to curb the component count in MLI structure. In this paper, a new topology is developed with a perspective to wane the switch count, which also has the ability of working in both symmetrical and asymmetrical modes. The performance of the proposed segmented ladder-structured MLI (SLSMLI) topology is substantiated with simulation study and experimentation. [ABSTRACT FROM AUTHOR]

In this paper, a new method is presented for joint estimation of delay and Doppler in bistatic radars by using model-based signal processing framework. In the proposed method, the time history of each cell in ambiguity function is modeled as a stochastic process consisting of a stationary component caused by clutter and noise as well as a possible transient component which is caused by a target. Then some cells are indicated as candidates for being targeted based on estimating the higher order statistics of the above stochastic processes. Finally, the spatial processing scheme is performed to prune false candidates. To evaluate the proposed method, its performance is simulated under two different scenarios (i.e., slow and fast moving targets) which have been inspirited from real conditions. Comparison of the results obtained from the proposed method with its alternatives, shows its better performance in such a way that it detects fast targets at least 8% better than the best among all examined methods. Furthermore, the proposed method detects slow targets at least 4.3% better than the best among all examined methods. Both of the above superiorities are obtained in those conditions while the false alarm of the proposed method does not show the meaningful difference against other examined algorithms. [ABSTRACT FROM AUTHOR]

In multi-carrier differential chaos shift keying (MC-DCSK) system, channel noises pollute both the reference and data signals, resulting in deteriorated performance. To reduce noises in received signals in MC-DCSK, a novel noise reduction MC-DCSK (NR-MC-DCSK) system is proposed in this paper. The proposed system utilizes duplicated chaotic samples, rather than different ones, as the reference. At the receiver side, identical samples can be averaged before correlation detection, which helps decrease the noise interferences and thus brings performance improvement. Theoretical bit error rate (BER) expressions are derived and verified by simulation results for additive white Gaussian noise and multipath Rayleigh fading channels. Finally, comparisons to MC-DCSK and other DCSK-based systems are given to confirm the superiority of the proposed system in BER performance. [ABSTRACT FROM AUTHOR]

Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy. [ABSTRACT FROM AUTHOR]

Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8). [ABSTRACT FROM AUTHOR]

This paper presents, a novel digital foreground calibration technique in order to reduce the effects of timing-skew in time-interleaved analog-to-digital converters (ADCs). The proposed technique implementation is simple and helps to achieve very low power consumption. This technique is based on the using of a simple reference comparator which is synchronized by one of sub-channels in each cycle of calibration. Also the detection and correction are implemented by a simple LMS loop that guarantee the convergence of algorithm. Finally, simulation results show that the new approach method can effectively correct timing errors for a specified input signal, and achieves a low power consumption, low computational complexity and high convergence speed and also verify theoretical equations for it. [ABSTRACT FROM AUTHOR]

To extend the existing knowledge on first-order voltage-mode all-pass filters, this paper presents two novel first-order voltage-mode all-pass sections, each employing single fully differential second-generation current conveyor (FDCCII) being used as the newly obtained fully differential voltage conveyor (FDVC), a resistor and a grounded capacitor. Both the proposed circuits possess high-input and low-output impedance feature, which makes the proposed circuits ideal for voltage-mode systems. Non-ideal study along with simulation results is given for validation. [ABSTRACT FROM AUTHOR]

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch-driver structure is designed to enable the effectiveness of the GC and provide sufficient driving ca-pability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch-driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400MS/s. The measured INL and DNL Eire both less than ±0.6 LSB. [ABSTRACT FROM AUTHOR]

This paper represents a new enhanced Colpitts oscillator, which is designed based on gm-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, the differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using 0.18 /im technology and is simulated under 1.8 V supply voltage in advanced design system (ADS). Simulations show the output phase noise of --140 dBc/Hz at 1 MHz offset frequency when the operating frequency is 1 GHz. [ABSTRACT FROM AUTHOR]

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation. [ABSTRACT FROM AUTHOR]

High reliability against undesirable effects is one of the key objectives in the design for Network-on-Chip (NoC). As a result, designing reliable and efficient routing method is highly desirable. This paper presents a novel turn model called NMad-y using one and two virtual channels along the - and -dimensions, respectively, and Adaptive and Fault-tolerant Routing Method (AFRM) which is designed based on the NMad-y turn model. AFRM can effectively tolerate multiple faulty routers and links in more complicated faulty situations by the link status of neighbor routers within two hops. AFRM is able to impose the reliability of network without losing the performance of network. Simulation results show that AFRM achieves better saturation throughput (0.83% on average) than a state-of-the-art fault-tolerant routing method and maintains high reliability of more than 97.43% on average. [ABSTRACT FROM AUTHOR]

This paper describes new sleep-based positive feedback source-coupled logic (PFSCL) tri-state inverter/buffer topologies. The tri-state behavior is obtained by disconnecting the circuit from both power supply and ground. This is achieved by placing additional transistors, driving the load transistor to cut off or disabling the current source. The combination of the three methods results in six new topologies. The functionality and performance of the proposed topologies is studied through SPICE simulations. A comparison with available sleep-based PFSCL tri-state buffer circuit shows a maximum reduction of 11% and 60% in the propagation delay and output enable time, respectively. The usefulness of the proposed topologies is illustrated through bus and D latch implementation. [ABSTRACT FROM AUTHOR]

This paper deals with the flux detection of squirrel cage induction generator (SCIG) in wind power. A novel observer named impulsive observer is presented to estimate the states of SCIG. Conditions for the existence of the impulsive observer are established by using linear matrix inequalities. A realization for the observer in SCIG is proposed. Simulation results are provided to show the validation of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic more energy efficient than conventional CMOS logic. [ABSTRACT FROM AUTHOR]

Nowadays, many simulations, implementations, synchronization and secure communication applications of chaotic circuits have been introduced in literature. However, electronics circuit design and implementation of nonlinear Sprott Case H chaotic system and its synchronization were not found in the literature. In this paper, numerical model, electronics circuit simulation and implementation electronics circuits of the Sprott Case H chaotic system and its synchro-nization by the method of Pecora and Carroll (P--C) complete replacement (CR) were per-formed. The simulation and implementation results showed that the Sprott Case H chaotic system can be synchronized and thus can be used for secure communication and encryption applications. [ABSTRACT FROM AUTHOR]

This paper proposes an isolated multi transformer cell inverter employing several transformer cells. Some of the cells contain two unidirectional switches that generate two voltage levels and only last cell has five switches that provide five voltage levels. The proposed inverter configuration reduces a number of switches compared with both traditional cascaded transformer multilevel inverter and other multi transformer inverters including six switches in last cell. Also, a prototype has been implemented using DSP-based processor provides a high number of output levels in symmetric and asymmetric states. The operation and performance of the suggested inverter has been proved by simulation result and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a multiband low-noise amplifier (LNA) with capability of band tuning is proposed to support the Mobile WiMAX (IEEE 802.16e) standard associated with a large IIP3 at RF frequencies using multi-gated linearization techniques. Proposed LNA architecture has been optimized in terms of linearity based on a comparative analysis between four tunable LNA structures. In addition, a general survey is performed on linearization techniques (multiple-gated transistors, Derivative Superposition (DS), Modified DS). Proposed LNA is constituted of multi-gated linearization technique. Design and simulations have been realized in 0.13 μm RF CMOS process considering a power supply of 1.2 V. Proposed LNA exhibits an IIP3 of +8.8 dBm, +14.3 dBm, and +6.4 dBm at the lower, middle, and upper bands of WIMAX, respectively. It results in a power gain of 10 dB, a noise figure below 2.5 dB and S11 of -11.5 dB, -8.6 dB, and -12.7 dB at the lower, middle, and upper bands. The related power dissipations are 10 mW, 9.9 mW, and 9.4 mW at the lower, middle, and upper bands, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel low power consumption, low phase noise, and high tuning range CMOS cross-coupled voltage-controlled oscillator (VCO). Using common mode double-pseudo-resistance technique in the proposed circuit leads to low power dissipation without degrading the phase noise. Additionally, band-switching capacitor array is employed in order to increase the tuning range. The schematic circuit of the proposed VCO is simulated in 0.18 μm 1P6M CMOS process and simulation results show high efficiency of the proposed circuit. The overall tuning frequency range is from 1.7 GHz to 3.18 GHz (59%) with tuning voltage variation range from 0 V to 1.5 V. The proposed VCO circuit has phase noise of -102.6 and -124.3 dBc/Hz at 100 KHz and 1 MHz offset frequency from the carrier, respectively, while consumes 1.98 mW power at 1.5 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents floating gate MOSFET (FGMOS)-based second generation differential voltage current conveyor (DVCCII) at low voltage levels. In analog circuit design, the FGMOS transistors are very often used in low voltage circuits, where the reduction obtained in the transistor apparent threshold voltage is of great importance. The given circuit provides very high input impedance at its Y-terminals, low output impedance at X-terminal and high impedance at Z-terminals and consumes less power. This circuit is a powerful building block, especially for applications demanding differential or floating inputs. The circuit behavior has been verified using PSpice simulations for 0.5 μm technology and indicates the excellent performance. [ABSTRACT FROM AUTHOR]

In this paper, a general electronically tunable resistorless biquad, which realizes current ratio transfer function using current backward transconductance amplifiers is proposed. The biquad contains only two active components and two grounded capacitors, which make it convenient for production by the integrated circuit technology. The proposed biquad realizes all of the basic second order filter characteristics: low pass, high pass, band pass, band reject, and finally all pass. It is convenient for cascading with other similar biquads as well as with any two-port circuit with low impedance input to achieve higher order filter characteristics. The simulations that are performed using PSPICE simulator exhibit satisfactory results coherent with the theory. [ABSTRACT FROM AUTHOR]

Resistance spot welding is a major metal connecting method in vehicle and other domestic electronic domains. Among all the welding techniques, the spot welding inverter is an important direction at the present time. The high nonlinearity and strongly coupled multiple parameters in the resistance spot welding process challenge the classical control theory based on some specific conditions and ideal assumptions, which in real practice obstacle the high-quality welding. This paper put the fuzzy neural network into a constant-current-controlled spot welding inverter, where the welding current peak and its variation are adopted as the input parameters and the duty ratio of the switches is regarded as the output. Eventually a five-layer feed-forward network was constructed, back propagation (BP) algorithm was applied to revise the adjustable parameters in the network, and a mathematical model was established to obtain the training samples serving for the network. The ultimate precision could reach 1.75%, the relative control error is 2.28% with strong external disturbances, the overmodulation is 3.35%, and the total modulating period is seven switching period, which indicated that the proposed algorithm has good performance. [ABSTRACT FROM AUTHOR]

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP). [ABSTRACT FROM AUTHOR]

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the error performance of the first detected symbol that causes error propagation, the proposed algorithm achieves a considerable performance gain compared with the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by a simulation. In the case of a 16QAM MIMO-SM system with 4 transmit and 4 receive (4 × 4) antennas, at BER = 10-3 the proposed algorithm results in a gain improvement of about 2.5-13.5 dB over the previous algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18 μm 1.8 V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly. [ABSTRACT FROM AUTHOR]

A number of configurations for realizing voltage-mode (VM) biquads using op-amps and OTAs have been presented in the literature, however, none of these provide the following desirable properties simultaneously: (i) realizability of all the five standard filters (namely; low pass, high pass, band pass, band stop and all pass), (ii) tunability of all the three filter parameters (namely; ω0, bandwidth or Q0 and gain) and (iii) not requiring any realization condition in any of the five filter responses. This paper presents a new configuration which does possess all the above mentioned desirable properties simultaneously while using only two internally-compensated type op-amps and a reasonable number of OTAs. The workability of the new configuration has been demonstrated by SPICE simulations based upon CMOS Op-amp and CMOS OTAs. [ABSTRACT FROM AUTHOR]

In this paper, novel low and high frequency performance improvement techniques are proposed. High frequency performance improvement method is based on the single pole effect reduction/completely elimination by creating a corresponding zero while a low one is based on reduction/elimination of Z terminal parasitic resistors. Therefore, two grounded capacitance multipliers, three grounded inductor simulators, a floating inductor and a voltage-mode (VM) universal filter using second-generation current conveyors (CCIIs) are used to explain the developed methods. One of the grounded inductor simulators, floating simulated inductor and VM biquad are novel. Further, both of the new simulated inductors use a grounded capacitor; accordingly, they are suitable for IC fabrication. However, all the proposed circuits need a single matching condition. A number of simulations through PSPICE program and experimental tests are accomplished to demonstrate the workability, performance and effectiveness. [ABSTRACT FROM AUTHOR]

It is well known that a floating inductor circuit is realized from a grounded inductor circuit by replacing the operational amplifier by a floating operational transconductance amplifier. This idea is extended to transform current conveyor grounded inductors to floating inductors by replacing the current conveyor by the recently introduced floating current conveyor. Several examples are considered and simulation results are given to support the theory. Although the paper is partially a review in nature it includes several new realizations of floating inductors. [ABSTRACT FROM AUTHOR]

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step. [ABSTRACT FROM AUTHOR]

This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented. [ABSTRACT FROM AUTHOR]

In this paper, a Tow–Thomas biquadratic filter designed in square root domain is proposed. The presented filter is constructed with a lossy integrator, a lossless integrator, and a summer block. To the best knowledge of the authors, the filter is the first square root domain Tow–Thomas filter in the literature. The state space synthesis method is used to design the biquadratic filter. The filter operated at 2.5 V supply voltage is simulated by using SPICE simulation program with 0.25 μm TSMC CMOS model parameters. Simulation results are in good agreement with theoretical results that the cut-off frequency and quality factor of the filter are tunable electronically. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS current controlled current differencing buffered amplifier (C-CDBA) realization is presented. Also, a new first-order all-pass filter that compensates for some C-CDBA non-idealities is given as an application example. The all-pass filter circuit has low output impedance for easy cascadability and it can be made electronically tunable using the proposed C-CDBA implementation. The theoretical results are verified with SPICE simulations. [ABSTRACT FROM AUTHOR]

In this paper we define a new class of the almost orthogonal filters. These filters are a generalization of the classical orthogonal filters commonly used in the circuit theory, control system theory, signal processing and process identification. Almost orthogonal filters generate the series of almost orthogonal Legendre functions on the interval (0, ∞). They can be successfully used for the analysis, synthesis and designing of imperfect technical systems. They can also be used for approximation of arbitrary functions on (0, ∞). A new method for obtaining the models of imperfect systems is presented as well. Simulations were performed in order to validate the theoretical results and the comparison of new filters with classical filters is given. [ABSTRACT FROM AUTHOR]

This paper presents an efficient redundancy removal technique for hierarchical optimization of FSM networks. In this technique, we first remove redundant transitions from the state transition graph (STG) of the driven FSM, M2, of the cascaded network by applying a reachability analysis to the composite machine, M1 → M2, once and for all. Then, a k-wise complete test suite for M2 is generated from the new STG of the driven FSM. Redundancy identification consists of two phases. In the first phase, almost all of the detectable stuck-at faults are identified by fault simulation using the k-wise test suite. During the second phase, each fault f that is undetected by k-wise tests is injected in M2 to obtain $M_2^f$ in the topologically sorted order one by one. Then the equivalence check of two FSMs M2 and $M_2^f$ in the environment where $M_2 (M_2^f)$ is driven by M1 is done. If a fault is found to be undetectable in the second phase, it is a redundant fault and kept in M2 ($M_2^f$ is taken as M2). Finally, simultaneous removal of redundant faults is done at logic level. We present experimental results to provide a comparison of the data produced by the state-of-the-art FSM network optimizer and show the effectiveness of our approach. [ABSTRACT FROM AUTHOR]

A new log-domain building block for log-domain filter design is proposed in this paper. This block realizes a positive impedance inverter (gyrator) by using the log-domain wave method. A simple procedure for log-domain filter development, using the proposed block, is outlined. This method results in circuits, which are simple in structure and very easy to design. An example of a second-order bandpass filter is given and its functionality is verified through simulations. [ABSTRACT FROM AUTHOR]

In this paper, the design of differential log-domain wave filters is outlined which is based on the log-domain wave technique. The differential configuration is achieved by introducing the differential log-domain wave equivalent. The resulting filters inherit the good characteristics of the wave active filters, are very modular and easy to design. The method is demonstrated by a design example and its validity is verified through simulations results. [ABSTRACT FROM AUTHOR]

The present paper describes a new arrangement that combines in a single unit a rectifier filter and a dc–dc converter. The performances are further improved by magnetically coupling the two inductors contained in the circuit. The filter and the dc–dc converter unit behave as a dc current source. Simulation and experimental results strengthen the theoretical approach. [ABSTRACT FROM AUTHOR]

This paper presents a compact second-order bandpass filter developed by combining the well-known flipped voltage follower circuit as a transconductance network with two capacitors. Operated in the subthreshold region, the filter's center frequency can be adjusted linearly by varying the bias current. Post-layout simulation using a 0.35-m CMOS process confirms the suitability of the proposed filter in low-voltage, low-power environment. [ABSTRACT FROM AUTHOR]