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This column discusses the 2015 ISCA Influential Paper Award, which recognized "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations" by David Brooks, Vivek Tiwari, and Margaret Martonosi. [ABSTRACT FROM AUTHOR]

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency. [ABSTRACT FROM AUTHOR]

In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to their limited efficiency. Reinforcement learning has been proven to be a practical solution for cognitive jamming decision-making in the cognitive electronic warfare. In this paper, we proposed a radar-jamming decision-making algorithm based on an improved Q-Learning algorithm. This improved Q-Learning algorithm ameliorated the problem of overestimating the Q-value that exists in the Q-Learning algorithm by introducing a second Q-table. At the same time, we performed a comprehensive design and implementation based on the classical Q-Learning algorithm, deploying it to a Field Programmable Gate Array (FPGA) hardware. We decomposed the implementation of the reinforcement learning algorithm into individual steps and described each step using a hardware description language. Then, the reinforcement learning algorithm can be computed on FPGA by linking the logic modules with valid signals. Experiments show that the proposed Q-Learning algorithm obtains considerable improvement in performance over the classical Q-Learning algorithm. Additionally, they confirm that the FPGA hardware can achieve great efficiency improvement on the radar-jamming decision-making algorithm implementation. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths ( L r e f ), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model's validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed research method is strictly aimed at further practical applications. The authors present the design technique aimed at the effective implementation of the modeled concurrent control system within the FPGA device. The main goal is the reduction in the logic resources of the destination FPGA by adequate modeling and optimization of the system. The proposed idea is illustrated by a real-life application of the photovoltaic control system implemented in the FPGA device from Xilinx (Artix-7 family). A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent control system is optimized by the use of the authors' techniques. The complete design flow is shown, including the modeling of the system by an interpreted Petri net, its further transformation to the hardware description language, adequate logic optimization, and final implementation within the destination FPGA. The presented method is explained by a case study example of the photovoltaic control system and compared with the already known technique. The performed experiments indicated a very high effectiveness of the proposed technique. It is shown that the photovoltaic control system designed according to the presented method reduces the logic resources of the destination FPGA device by up to 28%. [ABSTRACT FROM AUTHOR]

This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 ×ilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard. [ABSTRACT FROM AUTHOR]

An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work's new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy. [ABSTRACT FROM AUTHOR]

This paper proposes an image encryption algorithm based on combined 1D chaotic maps. First, a permutation technique was applied. It was then reorganized into 1D matrices along the rows and columns respectively, which were then shuffled by computing the substituted position indices to obtain the scrambled image. Subsequently, a method of confusion of the scrambled image was used through another generated data map, combined with random sub‐matrices for diffusion, then resulting in an encrypted image. Finally, the proposed cryptosystem was implemented in a single kernel platform developed using the Nios II Software Build Tools processor for Eclipse. A hardware architecture was designed using the Qsys‐built tool which is available in the Quartus II 13.0sp1 environment. The developed single‐core system was implemented using the Cyclone IV EP4CE6E22C8. Robustness evaluation of the cryptosystem was performed through security analysis tests such as histogram analysis, correlation coefficient, differential analysis, and key space analysis to prove that it is of good quality, efficient, fast, and successfully resisting brute force attacks. The hardware performance analysis was also carried out. Then the cryptosystem is compared with those in the literature both in the hardware and security performance aspects. [ABSTRACT FROM AUTHOR]

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AI by AI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AI by AI using a 130 nm technology, marking a groundbreaking achievement as possibly the world's first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system's validity. [ABSTRACT FROM AUTHOR]

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far. [ABSTRACT FROM AUTHOR]

The subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages (HDLs) that prevent failures in the state register and in the input vector of the FSM. The tasks to be solved are as follows: development of description methods for FSM transitions from illegal states in case of failure in the state register, as well as for FSM transitions from each state in case of failure in the input vector; determination of FSM output vector values in case of the above failures; development of description styles for fault-tolerant FSMs; and investigation of the efficiency of the proposed description styles for faulttolerant FSMs. The methods used are: the theory of finite state machines, state encoding methods of FSMs, description styles of FSMs, and Verilog hardware description language. The following results were obtained: two styles of describing fault-tolerant FSMs have been developed, safe0 and safe1, which do not increase the area and do not decrease the performance of FSMs, and in some cases allow the area to be reduced (for some examples by a factor of 4.8) and increase the performance (for some examples by a factor of 2.355). In addition, the description styles of fault-tolerant FSMs neutralize design errors when transitions are described in each state but not for all possible values of input variables. Conclusions. In this paper, the problem of designing faulttolerant FSMs when the values of bits in the state register or in the input vector of the FSM change because of the negative external impact is described. Different ways of solving the problem at the level of FSM description in HDL are considered. Two description styles for fault-tolerant FSMs are proposed: safe0 and safe1. The fault tolerance of FSMs is provided in the following manner. When the input vector is not defined in the FSM specification for a specific state, the FSM will remain in the initial transition state, i.e. the FSM will not transit to another state. If the code of the illegal state is set in the state register, the FSM will transition to the start state. For all these faults, the safe0 style provides a zero output vector at the FSM output, whereas the safe1 style preserves the value of the previous output vector. A promising direction for future research seems to be the development of new styles and methods of FSM description, aimed at improving the FSM parameters (an area, a performance and a power consumption), as well as improving the reliability and fault tolerance of FSMs. [ABSTRACT FROM AUTHOR]

Currently, distributed real-time control systems need the creation of devices that perform online computing operations close to the sensor. The proposed online-computers of elementary mathematical functions can be used as components for the functional conversion of signals in the form of pulse streams received from measuring sensors with frequency output. Objective. The objective of the study is the development of mathematical, architectural and automata models for the design of bit-stream online-computers of elementary mathematical functions in order to create a unified approach to their design, due to which the accuracy of calculating functions can be increased, functional capabilities expanded, hardware costs reduced, and design efficiency increased. Method. Mathematical models of devices were developed using the method of forming increments of ascending step functions based on inverse functions with minimization of calculation error. Automata models of online-computers based on Moore’s Finite State Machine have been developed, the graph diagrams of which made it possible to ensure the clarity of function implementation algorithms, to increase visibility and invariance of implementation in formal languages of programming and hardware description. Results. The paper presents the results of research, development and practical approbation of design models of bit-stream onlinecomputers of power functions and root extraction function. A generalized architecture of an online-computer was proposed. Conclusions. The considered functional online-computers are effective from the point of view of calculation accuracy, simplicity of technical implementation, and universality of the architecture. [ABSTRACT FROM AUTHOR]

Scalability in hardware and/or software is an important factor for enhancing the performance of running processes as well as the throughput of the system of business organizations. This paper explores the need for scalability and issues related to extending the resources in order to ensure an improved and scaled-up Customer Relationship Management (CRM) architecture. The main contribution discussed in this paper is the proposal of a conceptual framework for measuring the process performance and throughput of the system beyond the selection of the type of scalability. Furthermore, this paper concerns the CRM system, as customer requests, their online transactions, and responses need a fast and efficient system. Taking into consideration all these factors, ultimately this paper proposed a customer-friendly framework for measuring the process performance and throughput of the system. Finally, the proposed framework’s steps are shown in an algorithm calculating process performance and throughput of the system. [ABSTRACT FROM PUBLISHER]

In this paper, the authors illustrate the design of the exponential function based on the conventional and scale free hyperbolic Coordinate Rotation Digital Computer (CORDIC) algorithm which are used in applications of the neural networks Very Large Scale Integrated circuit design. The CORDIC algorithm is introduced to design the function of the neural networks. The design of exponential function based on conventional and scale free hyperbolic CORDIC processor is coded in VHSIC (Very High Speed Integrated Circuit) hardware description language and their simulation and synthesis results are present in this paper. The Xilinx 13.1 software is used for the simulation and synthesis of code design. [ABSTRACT FROM AUTHOR]

Stereo vision is a well-known technique for acquiring depth information. In this paper, we propose a real-time high-quality stereo vision system in field-programmable gate array (FPGA). Using absolute difference-census cost initialization, cross-based cost aggregation, and semiglobal optimization, the system provides high-quality depth results for high-definition images. This is the first complete real-time hardware system that supports both cost aggregation on variable support regions and semiglobal optimization in FPGAs. Furthermore, the system is designed to be scaled with image resolution, disparity range, and parallelism degree for maximum parallel efficiency. We present the depth map quality on the Middlebury benchmark and some real-world scenarios with different image resolutions. The results show that our system performs the best among FPGA-based stereo vision systems and its accuracy is comparable with those of current top-performing software implementations. The first version of the system was demonstrated on an Altera Stratix-IV FPGA board, processing 1024 $\times $ 768 pixel images with 96 disparity levels at 67 frames/s. The system is then scaled up on a new Altera Stratix-V FPGA and the processing ability is enhanced to $1600 \times 1200$ pixel images with 128 disparity levels at 42 frames/s. [ABSTRACT FROM PUBLISHER]

The validation of the measurements quality after on-site diagnostic system installation is necessary in order to provide reliable data and output results. This topic is often neglected or not discussed in detail regarding measurement systems. In the paper recently installed system for soft X-ray measurements is described in introduction. The system is based on multichannel GEM detector and the data is collected and sent in special format to PC unit for further postprocessing. The unique feature of the system is the ability to compute final data based on raw data only. The raw data is selected upon algorithms by FPGA units. The FPGAs are connected to the analog frontend of the system and able to register all of the signals and collect the useful data. The interface used for data streaming is PCIe Gen2 x4 for each FPGA, therefore high throughput of the system is ensured. The paper then discusses the properties of the installation environment of the system and basic functionality mode. New features are described, both in theoretical and practical approach. New modes correspond to the data quality monitoring features implemented for the system, that provide extra information to the postprocessing stage and final algorithms. In the article is described also additional mode to perform hardware simulation of signals in a tokamak-like environment using FPGAs. The summary describes the implemented features of the data quality monitoring features and additional modes of the system. [ABSTRACT FROM AUTHOR]

FPGA-realization of a rotor position estimation algorithm based on a novel sliding mode observer (SMO) for permanent magnet synchronous motor (PMSM) drives is adopted in this paper. Comparing to the conventional SMO, the estimator based on the novel SMO is presented for reducing the chattering phenomenon and improving the estimated precision of the rotor position. However, a hybrid sensorless control system for PMSM drives using I- f startup method then a smooth transition to the novel SMO-based sensorless field oriented control (FOC) are also considered in this paper. In realization, a very high speed IC hardware description language (VHDL) is firstly introduced to describe the behavior of the adopted estimation and control algorithm which is called the sensorless control intellectual property (IP). Then, to verify the correctness of the designed VHDL code for the sensorless control IP, it will be downloaded to the FPGA, and an experimental system with a sensorless PMSM drive is set up and some experimental results are demonstrated. [ABSTRACT FROM AUTHOR]

Filter design in signal processing field plays a vital role in achieving low power dissipation, which is essential for portable gadgets. This paper proposes an effective flexible FIR filter structure, which is adaptive and utilizes multiply-accumulate (MAC) core. Most common algorithm for filter coefficient optimization includes least mean square (LMS) and recursive least square (RLS). Though the performance of the recursive least square (RLS) algorithm is superior as compared to the least mean square (LMS); because of higher arithmetic complexity in design, it has not been preferred for real time applications. The fundamental filter has used a LMS based tapped delay line filter, which is practically a feasible choice for adaptive filtering algorithm in order to attain lesser computation. In the proposed work, the adjustable coefficient filters using an optimized LMS approach has been implemented for the utilization of determining the unexplored system. The filter tap considered here is a 32-tap and its analysis and synthesis has been carried out using hardware description language (HDL) programming and synthesized in field programmable gate array (FPGA) devices. The placement and post routing design has offered good performance in terms of utilized resources. The implemented filter architecture requires 80% reduction in resources and has enhanced the clock frequency by about five times when examined with the reported architecture. [ABSTRACT FROM AUTHOR]

In present paper, the authors has proposed a new idea for synthesis of an asynchronous digital system, using locally clock method. Driving an asynchronous digital system is much complex than a synchronous one. The authors has proposed a new method for synthesis of an asynchronous digital system using Verilog HDL Hardware Description Language, and also, the implementation into FPGA (Field Programable Gate Arrays) devices, [1-4]. The proposed method presented in this paper has many features like: execution speed much better, maximize the combinational/sequential digital logic, maximize the design performances (speed, low power, size). The CK and the output signals must be free of logic hazard; The minimum propagation delay of CK signal through the digital combinational system must be greater than the maximum propagation delay for every logic circuit which implements the input/output signals. Once the CK signal is triggered it can be reseted without digital hazard. Using the improved design described above, the entire asynchronous digital system will work with work correctly. [ABSTRACT FROM AUTHOR]

To increase productivity in designing digital hardware components, high-level synthesis (HLS) is seen as the next step in raising the design abstraction level. However, the quality of results (QoRs) of HLS tools has tended to be behind those of manual register-transfer level (RTL) flows. In this paper, we survey the scientific literature published since 2010 about the QoR and productivity differences between the HLS and RTL design flows. Altogether, our survey spans 46 papers and 118 associated applications. Our results show that on average, the QoR of RTL flow is still better than that of the state-of-the-art HLS tools. However, the average development time with HLS tools is only a third of that of the RTL flow, and a designer obtains over four times as high productivity with HLS. Based on our findings, we also present a model case study to sum up the best practices in comparative studies between HLS and RTL. The outcome of our case study is also in line with the survey results, as using an HLS tool is seen to increase the productivity by a factor of six. In addition, to help close the QoR gap, we present a survey of literature focused on improving HLS. Our results let us conclude that HLS is currently a viable option for fast prototyping and for designs with short time to market. [ABSTRACT FROM AUTHOR]

The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This "conventional" template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool. [ABSTRACT FROM AUTHOR]

A digital dead-beat current controller for voltage source converters is presented in this paper. The control structure is specified in a digital hardware description language, synthesized, and deployed on a field-programmable gate array chip. By updating, with negligible computation delay, the duty cycle twice in a switching period, the reference current error is nulled in half a modulation period, so that the controller's small-signal bandwidth is maximized. In addition, due to a simple transient detection circuit, the large-signal response delay is reduced to a small fraction of the modulation period, which is determined by the chosen current signal oversampling rate. The controller can effectively support different voltage-source inverter applications, such as active filters, uninterruptible power supplies, microgrid distributed energy resource controllers, and dc–dc converter applications, including interface converters for renewable energy sources, laboratory battery chargers, and electronic welding machines. [ABSTRACT FROM AUTHOR]

Universal filtered multicarrier (UFMC) is a low complexity promising waveform that provides quasi-orthogonal property among subcarriers. In addition, it can achieve much better out-of-band emission performance than orthogonal frequency division multiplexing (OFDM) system. Authors have proposed a hardware platform to implement a UFMC transmitter in this paper. Highly reduced complexity schemes for IFFT, filtering, and spectrum shifting are realized on actual hardware. This helps to achieve overall architecture of the transmitter at the cost of minimal FPGA resource usage. Hence, the overall design uses only 1038 slice registers, 1154 slice LUTs, and 64 multipliers of Xilinx Virtex-7 XC7VX330t device. A throughput of 773.5 Msamples/sec at an operational frequency of 364 MHz is achieved. This throughput is adequate for processing 50 Physical Resource Blocks (PRB) of LTE 10 MHz channelization in required time. The presented architecture provides a latency of only 2% of one LTE 10MHz channelization symbol due to the implementation of pipelining at different levels. Although the presented hardware design in its current form meets LTE 10MHz channelization throughput requirements, further increase in throughput is possible due to the scalable nature of the architecture. To the best of our knowledge, this work is first ever FPGA solution for UFMC transmitter presented in the literature. [ABSTRACT FROM AUTHOR]

Outsourcing of the chip product chain makes hardware vulnerable to be attacked. For example, an attacker who has access to hardware fabrication process can alter the genuine hardware with the insertion of concealed hardware elements [hardware Trojan (HT)]. Therefore, microelectronic circuit HT detection becomes a key step of chip production. A self-reference-based power-analysis microelectronic circuit HT detection methodology is proposed in this paper. The detection method is implemented in 90-nm CMOS process. Based on simulation results, our proposed technique can detect HTs with areas that are 0.013% of the host-circuitry. ISCAS benchmarks are used to evaluate efficiency of the developed method. [ABSTRACT FROM PUBLISHER]

In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact that the probabilities can be evaluated concurrently with the parsing during the parse table construction by extending the fundamental parsing operation proposed by Chiang & Fu. Using this extended operation, an efficient architecture is presented based on Earley's parallel algorithm, which given an input string, generates the parse table while evaluating concurrently the probabilities of the generated dotted grammar rules in the table. Based on this architecture, a platform has been implemented that automatically generates the hardware design of the parser given a SCFG. The platform is suitable for embedded systems applications where a natural language interface is required or in pattern recognition tasks. The proposed hardware platform has been tested for various SCFGs and was compared with previously presented hardware parser for SCFGs based on Earley's parallel algorithm. The hardware generated by the proposed platform is much less complicated than the one of comparison and succeeds a speed-up of one order of magnitude. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method for monitoring surface defects like cracks in highly loaded structures. This method is based on the ability of surface cracks to open under the influence of external loads, thus causing the appearance of stresses and tears in the sensitive element—thin films that were deposited on the surface of the test object. We developed a system for monitoring surface defects based on a distributed crack sensor, the functional scheme of the sensor and its design, the structural scheme and algorithm of the system operation, and its model as a VHDL (VHSIC (Very high speed integrated circuits) Hardware Description Language)-description. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient feature extraction accelerator design aimed at visual navigation. The hardware-oriented algorithmic modifications such as a circular-shaped sampling region and unified description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and balanced-leakage readout technique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a feature extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW with a clock frequency of 27 MHz at V dd = 470 mV, providing 3.5× better energy efficiency than previous state-of-the-art while extracting features from entire image. [ABSTRACT FROM PUBLISHER]

The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III. [ABSTRACT FROM AUTHOR]

The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at SoC level verification, these sequences take very long time to run. Similarly, currently users require strong knowledge of SystemVerilog UVM language to use UVM_REG model. Some limitations in current UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard UVM_REG API. This API is aimed at writing simpler directed tests which require less or no SystemVerilog/UVM understanding. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. We also developed our own register/memory sequences to address the SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG model. IP-XACT based tools are also developed to automatically generate all required verification environment files for using standard register model. [ABSTRACT FROM AUTHOR]

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits' logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems. [ABSTRACT FROM AUTHOR]

Web service is a technological solution for software interoperability that supports the seamless integration of diverse applications. In the vision of web service architecture, web services are described by the Web Service Description Language (WSDL), discovered through Universal Description, Discovery and Integration (UDDI) and communicate by the Simple Object Access Protocol (SOAP). Such a divination has never been fully accomplished yet. Although it was criticized that WSDL only has a syntactic definition of web services, but was not semantic, prior initiatives in semantic web services did not establish a correct methodology to resolve the problem. This paper examines the distinction and relationship between the syntactic and semantic definitions for web services that characterize different purposes in service computation. Further, this paper proposes that the semantics of web service are neutral and independent from the service interface definition, data types and platform. Such a conclusion can be a universal law in software engineering and service computing. Several use cases in the GIScience application are examined in this paper, while the formalization of geospatial services needs to be constructed by the GIScience community towards a comprehensive ontology of the conceptual definitions and relationships for geospatial computation. Advancements in semantic web services research will happen in domain science applications. [ABSTRACT FROM AUTHOR]

Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimized RNGs, so they are not commonly used in real-world designs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise xor operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resource–quality balance compared to previous FPGA-optimized generators, between the previous high-resource high-period LUT-FIFO RNGs and low-resource low-quality LUT-OPT RNGs, with quality comparable to the best software generators. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within this paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in this paper, backed up by an online set of very high speed integrated circuit hardware description language (VHDL) generators and test benches. [ABSTRACT FROM PUBLISHER]

This paper describes the verification of a real-time attitude determination algorithm during GPS attitude receiver hardware development. The GPS attitude receiver of 24 channels had been already developed in Surrey University. However 24 channels were not enough for practical usage. For this reason, a 48-channel attitude receiver with 12 channels for each antenna has been developed. To estimate attitude in real time, precise relative positions of the GPS antenna array have to be determined as rapidly as possible. However, the calculation load based on the conventional algorithm is too burdensome to perform using the RISC microprocessor. Therefore, in this paper, the cycle ambiguities of each base vector are resolved using SNUGLAD (Seoul Nat Univ GNSS Lab Attitude Determination), the design focus of which is to allow the receiver to estimate the 10 Hz onboard solutions. To keep precise solutions continuously, after ambiguity removal, cycle slip must be detected or isolated. Otherwise, the receiver would output erroneous solutions after a short signal blockage or fading of the GPS signal. To prevent this, we defined the cycle slip detection and repair scheme using a standard extended Kalman filter, which can detect and repair cycle slip within one cycle. As a result, this paper shows that time synchronized measurement with good quality and a reliable solution can be provided by the hardware developed with inexpensive chipsets and that this may be a possible cost efficient sensor for UAV or microsatellites. [ABSTRACT FROM AUTHOR]

This paper details the digital implementation of a new observation strategy of the flying capacitor voltages dedicated to stacked multicell converters (SMC). This particular topology relies on the use of flying capacitors so as to equally share the voltage constraint on several semiconductors and increase the number of output levels. However, the SMC appropriate operation is guaranteed by the stability of the flying capacitor voltage levels, and the current flow creates variations of those quantities. The idea is therefore to develop an accurate estimation technique that avoids the utilization of differential sensors and allows the active control of the intermediate voltages. The observation has to meet several criteria. It must particularly reproduce in a quasi- analog way the dynamic of those quantities to enable the proper operation of the active control algorithm. The actual research scope thus focuses on the sliding mode observation of the flying capacitor voltages by means of phase current measurements. This paper summarizes the observer design, its digitizing, and the field-programmable gate array (FPGA) implementation. It also presents an interesting Very High Speed Integrated Circuit Hard- ware Description Language (VHDL)-Saber Cosimulation tool that allows validating the VHDL code before being downloaded in the FPGA of the physical system. The last section illustrates and emphasizes the performance and ruggedness of the implemented algorithm through promising experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG algorithm first generates a test environment for each validation objective, which includes variable assignments, conditional statements, and arithmetic expressions in the hardware description language (HDL) description. The test environment for a given validation objective is a set of symbolic conditions that allow for full controllability and observability of that objective. After the RTL ATPG terminates, a back-end translator intelligently translates the test environments into validation vectors by filling in the necessary values. Since the observability of error effect is naturally handled by the RTL ATPG algorithm, this approach is superior to most existing validation methods, which only focus on the excitation of HDL constructs. A set of heuristics is proposed to utilize high-level circuit information to enhance the RTL ATPG algorithm and to maximize the validation efficiency. The RTL ATPG algorithm is also coupled with an improved RTL validation-coverage metric, which can help users to gain a higher degree of confidence on the quality of generated validation vectors. The usage of the coverage metric also results in the generation of compact vector sets. Experimental results on academic and industrial benchmark circuits demonstrate that our method is able to obtain very high design-error coverage in short execution times. [ABSTRACT FROM AUTHOR]

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling heterogeneous or multidiscipline systems. The paper has two objectives. The first one is modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e., discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Veriog-AMS languages and of the generated simulation results. The tools used are the Advance-MS from Mentor Graphics for VHDL-AMS and the AMS Simulator from Cadence Design Systems for Veriog-AMS. This paper shows that both languages offer effective means to describe and simulate multidiscipline systems, though using different descriptive approaches. It also highlights current tool limitations, since full language definitions are not yet supported. [ABSTRACT FROM AUTHOR]

The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the $64\times 64$ block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by $16\times 16$ block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a $4\times 4$ block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported $4096\times 2160$ at 30-frames/s video decoding at a 270-MHz operation frequency. [ABSTRACT FROM PUBLISHER]

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment. [ABSTRACT FROM AUTHOR]