Search

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si 0. 7 Ge 0. 3 material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high- k dielectric material HfO˙2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices. [ABSTRACT FROM AUTHOR]

Microfluidic biochips are extensively utilized in biochemistry procedures due to their low cost, high precision and efficiency when compared to traditional laboratory procedures. Recent, computer-aided design (CAD) techniques enable a high performance in digital microfluidic biochip design. A key part in digital microfluidic biochip CAD design is the biochip placement procedure which determines the physical location for biological reactions during the physical design. For the biochip physical design, multiple objects need to be considered, such as the size of the chip and the total operation time. In this paper, a multi-objective optimization is proposed based on Markov decision processes (MDPs). The proposed method is evaluated on a set of standard biochip benchmarks. Compared to existing works, experimental results show that the total operation time, the capacity for routing and the chip size can be optimized simultaneously. [ABSTRACT FROM AUTHOR]

In this paper, a developed structure for DC–DC quasi-Z-source (QZS) converters is proposed. First, the proposed two-stage structure is presented and analyzed. Then, the proposed structure is extended to n stages and its relations are calculated. Compared with other conventional structures, the proposed structure has higher voltage gain and higher reliability. The proposed topology is suitable for high power applications. To have the correct performance of conventional QZS converter, all impedance network elements must be intact. In the case of small failure in one of the elements, the operation of the whole system is disrupted. The proposed structure has high reliability because when one stage fails, the fault management system separates that stage from the other stages and the remaining stages continue to transmit power. In this paper, in addition to analyzing the operation of the proposed converter in different operating modes, calculations of voltage gain, voltage stresses across capacitors and reliability analysis are also presented. Reliability is calculated according to well-known Markov model. Moreover, a comprehensive comparison in terms of voltage gain and reliability is made between the proposed converter and the other conventional structures. Also, the rating values of inductors and capacitors are designed. Finally, experimental and simulation results are presented by using power system computer-aided design (PSCAD) software to verify the theories. [ABSTRACT FROM AUTHOR]

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle. [ABSTRACT FROM AUTHOR]

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the 'modular design efficiency' of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits. [ABSTRACT FROM AUTHOR]

In recent years, model order reduction (MOR) of interconnect system has become an important technique to reduce the computation complexity and improve the verification efficiency in the nanometer VLSI design. The Krylov subspaces techniques in existing MOR methods are efficient, and have become the methods of choice for generating small-scale macro-models of the large-scale multi-port RCL networks that arise in VLSI interconnect analysis. Although the Krylov subspace projection-based MOR methods have been widely studied over the past decade in the electrical computer-aided design community, all of them do not provide a best optimal solution in a given order. In this paper, a minimum norm least-squares solution for MOR by Krylov subspace methods is proposed. The method is based on generalized inverse (or pseudo-inverse) theory. This enables a new criterion for MOR-based Krylov subspace projection methods. Two numerical examples are used to test the PRIMA method based on the method proposed in this paper as a standard model. [ABSTRACT FROM AUTHOR]

Tight time-to-market pressure requires CAD tools to heavily involve component reuse, or intellectual property (IP) reuse, which imposes intense security concerns on IP protection. For the IP providers, it is critical to protect their products against unauthorized reproduction. Thus, circuit layout fingerprinting becomes quite important which helps the IP providers to detect which user distributes the illegal IPs. However, previous works addressing the circuit fingerprinting all have large area and runtime overhead. In this paper, a novel efficient discrete wavelet transform (DWT)-based key sensitive circuit layout fingerprinting technique using chaotic system is proposed. The new circuit layout fingerprinting technique targets to be applied after placement and routing, while before fabrication. Thus, it only slightly impacts the original design and introduces small runtime overhead as well. To further enhance the security, the chaotic system based on Fibonacci trans-formation is integrated. The experimental results demonstrate that our chaotic DWT-based technique largely outperforms a median-based technique for various attacks. The chaotic DWT-based technique improves the detection error rate by 68.5% for the gate swapping attack, by 65.8% for the random perturbation attack, by 54.8% for the partition-based perturbation attack and by 54.5% for the combined perturbation attack. In addition, the average wirelength overhead is only 0.0149% compared to the original design and the average runtime overhead is only 6.73 s. These demonstrate the effectiveness of our circuit layout fingerprinting technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel design procedure for class DE amplifier. And design curves of class DE amplifier with switch on resistance as functions of output Q, duty ratio, and load resistance are clarified. The feature of the proposed design procedure is that the waveform equations are never required. The design procedure requires only circuit equations and the design specifications. When circuit equations are derived, the other procedures for computations of design values are carried out with aid of computer. Therefore, it is possible to design class DE amplifier at any conditions, namely, at any output Q, any duty ratio, any switch on resistance and so on. By carrying out the circuit experiments, we denote that the experimental results agree with the calculation results quantitatively, and show the validity of the proposed design procedure. [ABSTRACT FROM AUTHOR]

Traditionally, magnetic component design has been based on power frequency transformers with sinusoidal excitation. However, the movement towards higher density integrated circuits means that reductions in the size of magnetic components must be achieved by operating at higher frequencies, mainly through nonsinusoidal switching circuits. As this trend continues, computing tools are required to carry out designs of magnetic components that also allow evaluation of the high frequency losses in these components. A computer design package is described here that implements a robust transformer design methodology allowing customizable transformer geometries. The concept of a critical frequency is a vital part of this methodology. In addition, the winding choice at high frequencies is optimized to give the most accurate results for the best possible speed. This paper includes a description of the software design processes used and describes the main aspects that were incorporated into the system. [ABSTRACT FROM AUTHOR]

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework. [ABSTRACT FROM AUTHOR]

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process. [ABSTRACT FROM AUTHOR]

In this paper, Ultra-Wideband (UWB) filters at 6–18 GHz are designed that can reduce undesired frequency responses at lower and upper frequency bands to less than − 20 dB. Arbitrary load impedances are considered in the design of these filters. The structure of these filters is the combination of microstrip band-pass filters and Defected Ground Structures (DGSs) with multiple sections. The optimum circuit dimensions are calculated using a computer code which implements the Least Mean Squares (LMS) optimization method. Two design examples are included to illustrate this method. In these examples, eight-section DGS structures are employed to eliminate the unwanted upper frequency band responses. To ensure the correct performance of the designed filters, they are analyzed using full-wave methods and fabrication and the results of the measurement or full-wave analysis shows good agreement with the results of the computer code and the circuit model simulations. [ABSTRACT FROM AUTHOR]

Low-noise amplifiers (LNAs) are critical to a wide variety of electronic circuits. In the design phase preceding fabrication, an LNA needs to be designed for a given set of specifications (e.g., gain, noise-figure, power consumption, etc.), which tend to be application-dependent. Typically, LNA design using commercial computer-aided design (CAD) tools can be human-intensive and requires a certain degree of expertise. This paper presents a systematic multi-phase CAD approach for the design of LNAs. In the first phase, a quick pre-analysis of the given LNA specifications is carried out leading to the selection of an appropriate LNA topology. In the second phase, an initial design of the LNA is generated employing an appropriate design procedure. Finally, the initial design is adjusted/fine-tuned so as to meet/exceed the given specifications, where necessary. The advantages of the proposed approach are shown through several practical LNA design examples in 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]

Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented. The research community tends to assume that the built-in functions provide accurate power figures. This blind-trust in the CAD tools, however, may lead to gross errors in power estimation. A generic methodology to accurately measure the power and energy consumption with the circuit simulators is described in this paper. An equation to calculate the device power consumption based on the different current conduction paths in a MOSFET is presented. An expression for the total power consumption of a complex circuit is derived by explicitly considering the different circuit terminals including the inputs, the outputs, and the body-contacts. Results indicate that the power measurements with the built-in functions of widely used commercial circuit simulators can introduce significant errors in a 65 nm CMOS technology. For deeply scaled nano-CMOS circuits, a conscious power and energy measurement with the proposed explicit methodology is recommended for an accurate pre-fabrication circuit characterization. [ABSTRACT FROM AUTHOR]

The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed. [ABSTRACT FROM AUTHOR]

By scaling the semiconductor industry to nano-scale era, design and prototyping cost of cell-based Application-Specific Integrated Circuits (ASICs) becomes more expensive and it makes Field Programmable Gate Arrays (FPGAs) more popular among designers. However, there is a gap between FPGAs and ASICs in terms of timing, dynamic power consumption and logic density. Three-dimensional integration, particularly in the full monolithic process, has been considered as a promising solution to reduce the performance gap of ASICs and FPGAs. In this paper, two new architectures for the monolithically integrated 3D-FPGAs are introduced. In order to exploit the great potentials of the suggested architectures, a new three-dimensional FPGA placement algorithm is proposed thereafter. The proposed placement algorithm, named JABE, is the first of its kind that enables designers to take advantages of the large number of vertical interconnections in the monolithically stacked 3D-FPGAs. Our experiments show a 24% timing improvement for the new architectures and CAD algorithms compared with the conventional TSV-based 3D-FPGAs and design flows. In addition, improvements in terms of the total wirelength and area footprint are reported for the proposed placement algorithms and new architectures. [ABSTRACT FROM AUTHOR]

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor. [ABSTRACT FROM AUTHOR]