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In non-isolated bidirectional DC-DC converters (NIBIDC), voltage output of buck/boost mode is incongruous at lower and higher end due to the existing gain. In this paper, a novel NIBIDC is designed in such a way that it enhances the gain in both buck and boost mode of operation. The proposed NIBIDC is employed with four power switches (MOSFET) with an anti-parallel diode embodied, four inductors and three capacitors used as passive elements. The current flow in parallel connected inductor improves the circuit competence. Voltage gain of NIBIDC in buck operation is lower than conventional cascaded bidirectional buck/boost converter (CCBBC) whereas the voltage gain is higher than CCBBC in boost mode. The switching stress is same while the efficiency of NIBIDC is more than CCBBC. The topology structure of the NIBIDC is simple and easy to control. The performance analysis under steady-state condition of the novel converter is carried out and a detailed comparison with CCBBC is done in connection to switching stress, converter efficiency and duty ratios to output power, etc. The operation details for proposed NIBIDC in both mode is verified/validated by experimenting with 20 V input for different duty ratios in charging and discharging state of a battery and the results infer to be identical with theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, the design methodology of a parallel-resonant converter for fuel cell applications in the electric vehicle is proposed in order to achieve high efficiency. Although the converter is unidirectional, it is interposed between the fuel cell and the DC link. Additionally, the converter is made up of two full bridges, an resonant filter and a planar transformer. The use of a high-frequency transformer enables to minimize the converter size and the weight, to produce a higher voltage in the secondary side from an input voltage (fuel cell) and to isolate the full bridges. Furthermore, the rectifier diodes operate with a zero-current switching. Therefore, an experimental converter prototype has been designed, simulated, built and tested in the laboratory. Finally, a prototype having 30V as an input and 150V as an output with 500W is designed to demonstrate and analyze the proposed converter. [ABSTRACT FROM AUTHOR]

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply. [ABSTRACT FROM AUTHOR]

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications. [ABSTRACT FROM AUTHOR]

The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. High power consumption can be reduced by properly increasing area. However, arbitrarily large area, namely high number of functional units (FU) in high-level view, dramatically increases IC cost. This paper describes a new dynamic-power aware High Level Synthesis data path approach that considers dynamic FU allocation while attempting to minimize area, power, or make a trade-off between them. The experimental results have shown that when the area is nearly the same, our approach delivers a 5.99% reduction in power consumption. And when the power consumption is nearly the same, a 11.81% reduction in total FU area occurs. And we can obtain different optimal power-area trade-off values by adjusting power and area ratios. [ABSTRACT FROM AUTHOR]