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In integrated circuit design, the analysis of wafer map patterns is critical to improve yield and detect manufacturing issues. We develop Wafer2Spike, an architecture for wafer map pattern classification using a spiking neural network (SNN), and demonstrate that a well-trained SNN achieves superior performance compared to deep neural network-based solutions. Wafer2Spike achieves an average classification accuracy of 98\% on the WM-811k wafer benchmark dataset. It is also superior to existing approaches for classifying defect patterns that are underrepresented in the original dataset. Wafer2Spike achieves this improved precision with great computational efficiency.

The patterns on wafer maps play a crucial role in helping engineers identify the causes of production issues during semiconductor manufacturing. In order to reduce costs and improve accuracy, automation technology is essential, and recent developments in deep learning have led to impressive results in wafer map pattern recognition. In this context, inspired by the effectiveness of semi-supervised learning and contrastive learning methods, we introduce an innovative approach that integrates the Mean Teacher framework with the supervised contrastive learning loss for enhanced wafer map pattern recognition. Our methodology not only addresses the nuances of wafer patterns but also tackles challenges arising from limited labeled data. To further refine the process, we address data imbalance in the wafer dataset by employing SMOTE and under-sampling techniques. We conduct a comprehensive analysis of our proposed method and demonstrate its effectiveness through experiments using real-world dataset WM811K obtained from semiconductor manufacturers. Compared to the baseline method, our method has achieved 5.46%, 6.68%, 5.42%, and 4.53% improvements in Accuracy, Precision, Recall, and F1 score, respectively., Comment: 5 pages,1 figures

In semiconductor manufacturing, wafer defect maps (WDMs) play a crucial role in diagnosing issues and enhancing process yields by revealing critical defect patterns. However, accurately categorizing WDM defects presents significant challenges due to noisy data, unbalanced defect classes, and the complexity of failure modes. To address these challenges, this study proposes a novel method combining a self-encoder-based data augmentation technique with a convolutional neural network (CNN). By introducing noise into the latent space, the self-encoder enhances data diversity and mitigates class imbalance, thereby improving the model's generalization capabilities. The augmented dataset is subsequently used to train the CNN, enabling it to deliver precise classification of both common and rare defect patterns. Experimental results on the WM-811K dataset demonstrate that the proposed method achieves a classification accuracy of 98.56%, surpassing Random Forest, SVM, and Logistic Regression by 19%, 21%, and 27%, respectively. These findings highlight the robustness and effectiveness of the proposed approach, offering a reliable solution for wafer defect detection and classification., Comment: 26 pages, 11 figures, including dataset preprocessing, proposed methods, and experimental results

Semiconductor heterojunctions are foundational to many advanced electronic and optoelectronic devices. However, achieving high-quality, lattice-mismatched interfaces remains challenging, limiting both scalability and device performance. Semiconductor grafting offers a promising solution by directly forming electrically active, lattice-mismatched heterojunctions between dissimilar materials. However, its scalability and uniformity at the wafer level have yet to be demonstrated. This work demonstrates the achievement of highly uniform, reproducible results across silicon, sapphire, and gallium nitride (GaN) substrates using wafer-scale semiconductor grafting. To illustrate this scalability, we conducted an in-depth study of a grafted Si/GaN heterojunction, examining band alignment through X-ray photoelectron spectroscopy and confirming crystallinity and interfacial integrity with scanning transmission electron microscopy. The resulting p-n diodes exhibit significantly enhanced electrical performance and wafer-scale uniformity compared to conventional approaches. This work establishes wafer-scale semiconductor grafting as a versatile and scalable technology, bridging the gap between laboratory-scale research and industrial manufacturing for heterogeneous semiconductor integration, and paving the way for novel, high-performance electronic and optoelectronic devices., Comment: 23 pages, 6 figures

The interaction of circularly polarized light with chiral matter and functional devices enables novel phenomena and applications. Recently, wafer-scale solid-state single-enantiomer carbon nanotube (CNT) films have become feasible and are emerging as a chiral photonic material platform thanks to their quantum-confinement-induced optical properties and facile scalable assembly. However, optical modeling, solver, and device design tools for such materials are non-existent. Here, we prepare wafer-scale single-enantiomer (6,5) and (11,-5) randomly oriented CNT films and create an optical material model based on measured experimental optical spectra. We also implement a highly-parallel graphic-processing-unit accelerated transfer matrix solver for general bi-anisotropic materials and layered structures. Further, we demonstrate reconfigurable chiral photonic devices in a heterostructure with phase change materials through machine learning-enabled efficient gradient-based inverse design and optimization. Our developed full stack of a chiral photonic material and device hardware platform and a corresponding high-performance differential-programming-enabled solver opens the door for future chiral photonic devices and applications based on single-enantiomer CNT films.

This work proposes a hybrid model- and data-based scheme for fault detection, isolation, and estimation (FDIE) for a class of wafer handler (WH) robots. The proposed hybrid scheme consists of: 1) a linear filter that simultaneously estimates system states and fault-induced signals from sensing and actuation data; and 2) a data-driven classifier, in the form of a support vector machine (SVM), that detects and isolates the fault type using estimates generated by the filter. We demonstrate the effectiveness of the scheme for two critical fault types for WH robots used in the semiconductor industry: broken-belt in the lower arm of the WH robot (an abrupt fault) and tilt in the robot arms (an incipient fault). We derive explicit models of the robot motion dynamics induced by these faults and test the diagnostics scheme in a realistic simulation-based case study. These case study results demonstrate that the proposed hybrid FDIE scheme achieves superior performance compared to purely data-driven methods.

As numerical simulations grow in size and complexity, they become increasingly resource-intensive in terms of time and energy. While specialized hardware accelerators often provide order-of-magnitude gains and are state of the art in other scientific fields, their availability and applicability in computational neuroscience is still limited. In this field, neuromorphic accelerators, particularly mixed-signal architectures like the BrainScaleS systems, offer the most significant performance benefits. These systems maintain a constant, accelerated emulation speed independent of network model and size. This is especially beneficial when traditional simulators reach their limits, such as when modeling complex neuron dynamics, incorporating plasticity mechanisms, or running long or repetitive experiments. However, the analog nature of these systems introduces new challenges. In this paper we demonstrate the capabilities and advantages of the BrainScaleS-1 system and how it can be used in combination with conventional software simulations. We report the emulation time and energy consumption for two biologically inspired networks adapted to the neuromorphic hardware substrate: a balanced random network based on Brunel and the cortical microcircuit from Potjans and Diesmann.

In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones., Comment: Accepted by EDTM 2025

Predicting the minimum operating voltage ($V_{min}$) of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing $V_{min}$ prediction methods often overlook various sources of variations in both training and deployment phases. Notably, the neglect of wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations, compounded by process variations, diminishes the accuracy, data efficiency, and reliability of $V_{min}$ predictors. To address this gap, we introduce a novel data-efficient $V_{min}$ prediction flow, termed restricted bias alignment (RBA), which incorporates a novel variation alignment technique. Our approach concurrently estimates inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. We empirically demonstrate RBA's effectiveness and data efficiency on an industrial 16nm automotive chip dataset.

Leveraging the advanced manufacturing capabilities of the semiconductor industry promises to help scale up silicon-based quantum processors by increasing yield, uniformity and integration. Recent studies of quantum dots fabricated on 300 mm wafer metal-oxide-semiconductor (MOS) processes have shown control and readout of individual spin qubits, yet quantum processors require two-qubit interactions to operate. Here, we use a 300 mm wafer MOS process customized for spin qubits and demonstrate coherent control of two electron spins using the spin-spin exchange interaction, forming the basis of an entangling gate such as $\sqrt{\text{SWAP}}$. We observe gate dephasing times of up to $T_2^{*}\approx500$ ns and a gate quality factor of 10. We further extend the coherence by up to an order of magnitude using an echo sequence. For readout, we introduce a dispersive readout technique, the radiofrequency electron cascade, that amplifies the signal while retaining the spin-projective nature of dispersive measurements. Our results demonstrate an industrial grade platform for two-qubit operations, alongside integration with dispersive sensing techniques.

In semiconductor manufacturing, the wafer dicing process is central yet vulnerable to defects that significantly impair yield - the proportion of defect-free chips. Deep neural networks are the current state of the art in (semi-)automated visual inspection. However, they are notoriously known to require a particularly large amount of data for model training. To address these challenges, we explore the application of generative adversarial networks (GAN) for image data augmentation and classification of semiconductor wafer dicing induced defects to enhance the variety and balance of training data for visual inspection systems. With this approach, synthetic yet realistic images are generated that mimic real-world dicing defects. We employ three different GAN variants for high-resolution image synthesis: Deep Convolutional GAN (DCGAN), CycleGAN, and StyleGAN3. Our work-in-progress results demonstrate that improved classification accuracies can be obtained, showing an average improvement of up to 23.1 % from 65.1 % (baseline experiment) to 88.2 % (DCGAN experiment) in balanced accuracy, which may enable yield optimization in production., Comment: Accepted for: 2024 IEEE 29th International Conference on Emerging Technologies and Factory Automation (ETFA)

Intelligence is key to advancing integrated circuit (IC) fabrication. Recent breakthroughs in Large Multimodal Models (LMMs) have unlocked unparalleled abilities in understanding images and text, fostering intelligent fabrication. Leveraging the power of LMMs, we introduce FabGPT, a customized IC fabrication large multimodal model for wafer defect knowledge query. FabGPT manifests expertise in conducting defect detection in Scanning Electron Microscope (SEM) images, performing root cause analysis, and providing expert question-answering (Q&A) on fabrication processes. FabGPT matches enhanced multimodal features to automatically detect minute defects under complex wafer backgrounds and reduce the subjectivity of manual threshold settings. Besides, the proposed modulation module and interactive corpus training strategy embed wafer defect knowledge into the pre-trained model, effectively balancing Q&A queries related to defect knowledge and original knowledge and mitigating the modality bias issues. Experiments on in-house fab data (SEM-WaD) show that our FabGPT achieves significant performance improvement in wafer defect detection and knowledge querying.

Existing high-performance computing (HPC) interconnection architectures are based on high-radix switches, which limits the injection/local performance and introduces latency/energy/cost overhead. The new wafer-scale packaging and high-speed wireline technologies provide high-density, low-latency, and high-bandwidth connectivity, thus promising to support direct-connected high-radix interconnection architecture. In this paper, we propose a wafer-based interconnection architecture called Switch-Less-Dragonfly-on-Wafers. By utilizing distributed high-bandwidth networks-on-chip-on-wafer, costly high-radix switches of the Dragonfly topology are eliminated while increasing the injection/local throughput and maintaining the global throughput. Based on the proposed architecture, we also introduce baseline and improved deadlock-free minimal/non-minimal routing algorithms with only one additional virtual channel. Extensive evaluations show that the Switch-Less-Dragonfly-on-Wafers outperforms the traditional switch-based Dragonfly in both cost and performance. Similar approaches can be applied to other switch-based direct topologies, thus promising to power future large-scale supercomputers.

The realisation of an universal quantum computer will require the operation of thousands to millions of qubits. The possibility of using existing industrial semiconductor fabrication techniques and infrastructure for up-scaling and reproducibility makes silicon based spin qubits one of the most promising platforms to achieve this goal. The implementation of the up to now largest semiconductor based quantum processor was realized in a silicon/silicon-germanium heterostructure known for its low charge noise, long qubit coherence times and fast driving speeds, but the high structural complexity creates challenges for industrial implementations. Here we demonstrate quantum dots hosted in a natural Si/SiGe heterostructure fully fabricated by an industrial 300$\,$mm semiconductor wafer process line from heterostructure growth to Co micromagnet monolithic integration. We report charge noise values below 2$\,\mathrm{\mu eV/\sqrt{Hz}}$, spin relaxation times of over 1$\,$s and coherence times $T_2^*$ and $T_2^H$ of 1$\,\mathrm{\mu s}$ and 50$\,\mathrm{\mu s}$ respectively, for quantum wells grown using natural silicon. Further, we achieve Rabi frequencies up to 5$\,$MHz and single qubit gate fidelities above 99$\,\%$. In addition to scalability, the high reproducibility of the 300$\,$mm processes enables the deterministic study of qubit metric dependencies on process parameters, which is essential for optimising qubit quality.

Transformer based Large Language Models (LLMs) have recently reached state of the art performance in Natural Language Processing (NLP) and Computer Vision (CV) domains. LLMs use the Multi-Headed Self-Attention (MHSA) mechanism to capture long-range global attention relationships among input words or image patches, drastically improving its performance over prior deep learning approaches. In this paper, we evaluate the performance of LLMs on the Cerebras Wafer Scale Engine (WSE). Cerebras WSE is a high performance computing system with 2.6 trillion transistors, 850,000 cores and 40 GB on-chip memory. Cerebras WSE's Sparse Linear Algebra Compute (SLAC) cores eliminates multiply-by-zeros operations and its 40 GB of on-chip memory is uniformly distributed among SLAC cores, enabling fast local access to model parameters. Moreover, Cerebras software configures routing between cores at runtime, optimizing communication overhead among cores. As LLMs are becoming more commonly used, new hardware architectures are needed to accelerate LLMs training and inference. We benchmark the effectiveness of this hardware architecture at accelerating LLMs training and inference. Additionally, we analyze if Cerebras WSE can scale the memory-wall associated with traditionally memory-bound compute tasks using its 20 PB/s high bandwidth memory. Furthermore, we examine the performance scalability of Cerebras WSE through a roofline model. By plotting performance metrics against computational intensity, we aim to assess their effectiveness at handling high compute-intensive LLMs training and inference tasks., Comment: IEEE HPEC 2024

We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented {\delta}-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or Hc2 (34.06 T boost in Hc2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications.

We report on the wafer scale fabrication of single mode low-loss lithium niobate on insulator waveguides utilizing a chemically amplified resist and an optimized dry etching method. The fabricated single mode waveguides are free of residuals and re-deposition, with measured losses for straight waveguides around 2 dB/m (0.02 dB/cm). We present on a method offering advantages for large-scale production due to its cost-effectiveness, faster writing time, and simplified processes. This work holds promise for advancing integrated photonics and optical communication technologies.

The emergence of the large language model~(LLM) poses an exponential growth of demand for computation throughput, memory capacity, and communication bandwidth. Such a demand growth has significantly surpassed the improvement of corresponding chip designs. With the advancement of fabrication and integration technologies, designers have been developing Wafer-Scale Chips~(WSCs) to scale up and exploit the limits of computation density, memory capacity, and communication bandwidth at the level of a single chip. Existing solutions have demonstrated the significant advantages of WSCs over traditional designs, showing potential to effectively support LLM workloads. Despite the benefits, exploring the early-stage design space of WSCs for LLMs is a crucial yet challenging task due to the enormous and complicated design space, time-consuming evaluation methods, and inefficient exploration strategies. To address these challenges, we propose Theseus, an efficient WSC design space exploration framework for LLMs. We construct the design space of WSCs with various constraints considering the unique characteristics of WSCs. We propose efficient evaluation methodologies for large-scale NoC-based WSCs and introduce multi-fidelity Bayesian optimization to efficiently explore the design space. Evaluation results demonstrate the efficiency of Theseus that the searched Pareto optimal results outperform GPU cluster and existing WSC designs by up to 62.8\%/73.7\% in performance and 38.6\%/42.4\% in power consumption for LLM training, while improving up to 23.2$\times$ and 15.7$\times$ for the performance and power of inference tasks. Furthermore, we conduct case studies to address the design tradeoffs in WSCs and provide insights to facilitate WSC designs for LLMs.

Whispering gallery mode (WGM) optomechanical resonators are a promising technology for the simultaneous control and measurement of optical and mechanical degrees of freedom at the nanoscale. They offer potential for use across a wide range of applications such as sensors and quantum transducers. Double-disk WGM resonators, which host strongly interacting mechanical and optical modes co-localized around their circumference, are particularly attractive due to their high optomechanical coupling. Large-scale integrated fabrication of silicon double-disk WGM resonators has not previously been demonstrated. In this work we present a process for the fabrication of double-layer silicon-on-insulator wafers, which we then use to fabricate functional optomechanical double silicon disk resonators with on-chip optical coupling. The integrated devices present an experimentally observed optical quality factors of the order of 10^5 and a single-photon optomechanical coupling of approximately 15 kHz.

Chiral carbon nanotubes (CNTs) are direct-gap semiconductors with optical properties governed by one-dimensional excitons with enormous oscillator strengths. Each species of chiral CNTs has an enantiomeric pair of left- and right-handed CNTs with nearly identical properties, but enantiomer-dependent phenomena can emerge, especially in nonlinear optical processes. Theoretical studies have predicted strong second-order nonlinearities for chiral CNTs, but there has been no experimental verification due to the lack of macroscopically ordered assemblies of single-enantiomer chiral CNTs. Here for the first time, we report the synthesis of centimeter-scale films of densely packed and aligned single-enantiomer chiral CNTs that exhibit micro-fabrication compatibility. We observe giant second harmonic generation (SHG) emission from the chiral CNT film, which originates from the intrinsic chirality and inversion symmetry breaking of the atomic structure of chiral CNTs. The observed value of the dominant element of the second-order nonlinear optical susceptibility tensor reaches $1.5\times 10^{3}$ pm/V at a pump wavelength of 1030 nm, corresponding to the lowest-energy excitonic resonance. Our calculations based on many-body theory correctly estimate the spectrum and magnitude of such excitonically enhanced optical nonlinearity. These results are promising for developing scalable chiral-CNT electronics, nonlinear photonics and photonic quantum computing.

Distributed Deep Neural Network (DNN) training is a technique to reduce the training overhead by distributing the training tasks into multiple accelerators, according to a parallelization strategy. However, high-performance compute and interconnects are needed for maximum speed-up and linear scaling of the system. Wafer-scale systems are a promising technology that allows for tightly integrating high-end accelerators with high-speed wafer-scale interconnects, making it an attractive platform for distributed training. However, the wafer-scale interconnect should offer high performance and flexibility for various parallelization strategies to enable maximum optimizations for compute and memory usage. In this paper, we propose FRED, a wafer-scale interconnect that is tailored for the high-BW requirements of wafer-scale networks and can efficiently execute communication patterns of different parallelization strategies. Furthermore, FRED supports in-switch collective communication execution that reduces the network traffic by approximately 2X. Our results show that FRED can improve the average end-to-end training time of ResNet-152, Transformer-17B, GPT-3, and Transformer-1T by 1.76X, 1.87X, 1.34X, and 1.4X, respectively when compared to a baseline waferscale 2D-Mesh fabric.

The development of manufacturable and scalable integrated nonlinear photonic materials is driving key technologies in diverse areas such as high-speed communications, signal processing, sensing, and quantum information. Here, we demonstrate a novel nonlinear platform -- InGaP-on-insulator -- optimized for visible-to-telecommunication wavelength $\chi^{\left(2\right)}$ nonlinear optical processes. In this work, we detail our 100-mm wafer-scale InGaP-on-insulator fabrication process realized via wafer bonding, optical lithography, and dry-etching techniques. The resulting wafers yield 1000s of components in each fabrication cycle, with initial designs that include chip-to-fiber couplers, 12.5-cm-long nested spiral waveguides, and arrays of microring resonators with free-spectral ranges spanning 400-900 GHz. We demonstrate intrinsic resonator quality factors as high as 324,000 (440,000) for single-resonance (split-resonance) modes near 1550 nm corresponding to 1.56 dB cm$^{-1}$ (1.22 dB cm$^{-1}$) propagation loss. We analyze the loss versus waveguide width and resonator radius to establish the operating regime for optimal 775-to-1550 nm phase matching. By combining the high $\chi^{\left(2\right)}$ and $\chi^{\left(3\right)}$ optical nonlinearity of InGaP with wafer-scale fabrication and low propagation loss, these results open promising possibilities for entangled-photon, multi-photon, and squeezed light generation.

The ability to design and dynamically control chiroptical responses in solid-state matter at wafer scale enables new opportunities in various areas. Here we present a full stack of computer-aided designs and experimental implementations of a dynamically programmable, unified, scalable chiroptical heterostructure containing twisted aligned one-dimensional (1D) carbon nanotubes (CNTs) and non-volatile phase change materials (PCMs). We develop a software infrastructure based on high-performance machine learning frameworks, including differentiable programming and derivative-free optimization, to efficiently optimize the tunability of both excitonic reciprocal and linear-anisotropy-induced nonreciprocal circular dichroism (CD) responses. We experimentally implement designed heterostructures with wafer-scale self-assembled aligned CNTs and deposited PCMs. We dynamically program reciprocal and nonreciprocal CD responses by inducing phase transitions of PCMs, and nonreciprocal responses display polarity reversal of CD upon sample flipping in broadband spectral ranges. All experimental results agree with simulations. Further, we demonstrate that the vertical dimension of heterostructure is scalable with the number of stacking layers and aligned CNTs play dual roles - the layer to produce CD responses and the Joule heating electrode to electrically program PCMs. This heterostructure platform is versatile and expandable to a library of 1D nanomaterials and electro-optic materials for exploring novel chiral phenomena and photonic and optoelectronic devices.

We describe a process for fabricating a wafer-scale array of alkali metal vapor cells with low residual gas pressure. We show that by etching long, thin channels between the cells on the Si wafer surface, the residual gas pressure in the evacuated vapor cell can be reduced to below 0.5 kPa (4 Torr) with a yield above 50 %. The low residual gas pressure in these mass-producible alkali vapor cells can enable a new generation of low-cost chip-scale atomic devices such as vapor cell optical clocks, wavelength references, and Rydberg sensors.

Color center platforms have been at the forefront of quantum nanophotonics for applications in quantum networking, computing, and sensing. However, large-scale deployment of this technology has been stifled by a lack of ability to integrate photonic devices at scale while maintaining the properties of quantum emitters. We address this challenge in silicon carbide which has both commercially available wafer-scale substrates and is a host to color centers with desirable optical and spin properties. Using ion beam etching at an angle, we develop a 5-inch wafer process for the fabrication of triangular cross-section photonic devices in bulk 4H-SiC. The developed process has a variability in etch rate and etch angle of 5.4% and 2.9%, respectively. Furthermore, the integrated color centers maintain their optical properties after the etch, thus achieving the nanofabrication goal of wafer-scale nanofabrication in quantum-grade silicon carbide.