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Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) are preferred for realizing logic circuits at nanoscale dimensions along with a high level of integration and minimal energy consumption. Hamming code is a set of entropy codes used for error detection and correction in communication systems. Error detection and correction is carried out with the help of parity bits which are appended with the original bits. Designing a Hamming encoder in nanoscale has its own merits such as optimized area, reduced energy dissipation and lower QCA cost. This work proposes two QCA-based (7, 4) Hamming encoder designs; multilayer (proposed1) and coplanar (proposed-2) structure with area and energy analysis. Proposed-1 encoder has achieved reduction of cell area by 12.5 %, 34.58 % in terms of cell count, and reduction in total energy dissipation of 26.8 % when compared to reference encoder. Proposed2 encoder has achieved reduction of 18.75 % in area, 44.15 % in terms of cell count, and 16.5 % in total energy dissipation when compared to reference encoder. In terms of QCA cost, reduction of 12.5 % is achieved in case of proposed structures. The energy dissipated in the proposed designs is less compared to reference encoder. Proposed-2 structure is more efficient compared to multilayer and reference encoder in terms of cell count, cell area and QCA cost. The QCA circuits are realized in QCADesigner and analyzed energy in QCADesigner-E. [ABSTRACT FROM AUTHOR]