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A prototype RF probe card is assembled to test the feasibility of Pogo-pins as robust probe tips for the automized testing of multiple-port millimeter-wave circuits. A custom-made ceramic housing machined from a low-loss dielectric holds an array of 157 Pogo-pins, each with 2.9 mm-length in fixed positions. The ceramic housing is then mounted onto a probe-card PCB for power-loss measurements on two signal-ground Pogo-pin connections arbitrarily selected from the array. The probing results on a test circuit with a simple thru-line indicate a successful power transfer with a small insertion loss of less than 0.5 dB per single Pogo-pin connection up to 25 GHz. A new probe card design using shorter Pogo-pins is being prepared to extend the operation frequency to beyond 40 GHz.

In this present work, a highly damped deployable solar panel module was developed for application in the 3 U CubeSat. The solar panel proposed herein is effective in guaranteeing the structural safety of solar cells under a launch environment owing to the superior damping characteristics achieved using multilayered stiffeners with viscoelastic acrylic tapes. A holding and release action of the solar panel was achieved by a new version of spring-loaded pogo pin-based burn wire triggering mechanism. A demonstration model of high-damping solar panel assembly was fabricated and tested to validate the effectiveness of the design. The holding and release mechanism achieved using a pogo pin was functionally tested through solar panel deployment tests under ambient room temperature and a thermal vacuum environment. The design effectiveness and structural safety of the solar panel module were validated through qualification-level launch and in-orbit environment tests.

CubeSats are revolutionary to the space industry and are transforming space exploration which enables the next generation of scientists and engineers to complete all phases of space missions. Deployable solar panels have been widely used for the generation of enough power in CubeSats due to their limited volume area for solar cell integration. In general, the cable cutting release mechanism have been used in 1U-3U small satellites because of its simplicity and low cost. However, this mechanism has a low constraint force and is unable to apply constraints along the in-plane and out-of-plane directions. In this study, for the improvement of the conventional cable cutting mechanism, a spring-loaded pogo pin-based nichrome burn wire holding and release mechanism (HRM) was proposed and fabricated. The pogo pin constitutes an immensely attractive function for the holding and release mechanism of solar panels because it works as an electrical interface to provide power, a separation spring to initiate the reaction force to deploy the panels, and a status switch to determine deployments. In addition, the proposed mechanism guarantees the loading capability along the in-plane and out-of-plane directions of solar panels, the synchronous release of multiple panels, and a handling simplicity that differentiates it from the conventional mechanism. The design feasibility, structural safety, and reliability of the mechanism were verified through functionality tests and launch and on-orbit environmental tests. The proposed pogo pin-based holding and release mechanism would be equally applicable for other CubeSat deployable appendages.

A spring-loaded pogo pin as a holding and release mechanism of solar panels for cube satellite applications is proposed which functions as an electrical interface, a separation spring, and a status switch. The proposed mechanism has many advantages, including an increased loading capability, negligible induced shock level, synchronous release of multiple panels, and handling simplicity during integration. A demonstration model of the mechanism was fabricated and functionally tested under various test conditions such as different input voltages, different numbers of tightened nylon wires, and different temperatures (ranging from −40°C to 70°C).

Physical parameters of a pogo pin that can influence the pogo pin characteristic impedance are identified. A coupled impedance extraction method is used to extract the characteristic impedance of a pogo pin. An impedance matching technique is introduced, utilizing commercial software. A pin design experiment is presented, parameterizing the pogo pin geometry, optimizing the characteristic impedance to meet the S-Parameter requirements.

A high performance connector and USB3.1 gen2 co-design fabricated using pogo pin and new RF pin structure are presented. A prototype of the proposed pogo pin connector with a compact area size of 1.8mm pitch is implemented, and the pogo pin connector shows a wide operating bandwidth, making it easy to cover the USB 3.1 gen1 and gen2 for high speed connector operation.

Signal transmission characteristics of the barrel-less pogo pins are analyzed using 3-dimensional electromagnetic field simulation. To obtain better signal transmission, the insertion loss and the reflection loss of the pogo pins are calculated with various signal-ground pin assignments. The effects of the signal transmission characteristics of the pogo pins on the increase in the number of the ground pin are investigated. Their characteristic impedances (Z0) are also calculated to analyze the frequency response of the pins.

This paper presents a comparison of two different printed circuit board (PCB) via field designs for high density ATE pogo pin interconnects running at Gb/s data rates. The first design is a simple straight through, one-for-one, pogo pin to via design while the second is a higher performance via design that does a transformation of the pogo pin pitch. The higher performance design takes the non-uniform signal/ground pin map of the high density pogo block and translates it to a uniform signal-ground-signal topology to increase the useable bandwidth.

Integrated Circuit (IC) product test in semiconductor manufacturing industry is commonly conducted through the socket pogo pins contacting with the IC products. The socket pogo pins can be degraded due to repeatedly plugging-into and pulling-out from the socket. Degradation in socket pogo pins will greatly affect the accuracy of final test in semiconductor manufacturing, which in turn results in economic and reputation losses of manufacturers. How to rapidly and accurately detect the degraded pogo pins is still unresolved. In addition, the very huge data produced by a large amount of tester machines will further bring difficulties into degradation detection of socket pogo pins. Focusing on those existing problems in semiconductor manufacturing, this paper proposed a data driven framework with adopting data mining techniques to tackle them. This framework transforms the test data generated by manufacturing machines into human readable format and then analyzes them by data mining techniques, which empowers the manufacturing engineers to automatically detect the degraded socket pogo pins from the test data. Extensive experimental studies with real data were carried out and the results show great application prospect of the proposed framework.

In this paper we propose a simple, reusable and non-intrusive approach for programming the Zolertia-Z1 mote through the JTAG-port. Programming the Zolertia-Z1 mote is generally achieved by using the Contiki Boot Script Loader and a USB cable. However, complications arise when building programs which exceed the 64kB-boundary of program memory. Special care must be taken in order to fully utilize the 92kB of available memory. At one hand, a 20 bit compiler is needed to support the complete available memory. At the other hand, a JTAG connection must then be used in order to flash the program onto the MSP430-microcontroller of the Zolertia-Z1 mote. Solutions exist in the aim of facilitating the JTAG-programming. However, these solutions are generally not reliable or need an intrusive approach, or are prohibitively expensive. Therefore, we propose a non-intrusive, reusable and reliable solution based on pogo pins. The Pogo-Pin JTAG Programmer Box consists out of an adapter board and the box itself. The adapter board can be used separately from the box for one-time flashing. Using both at the same time ensures reliable consecutive reprogramming cycles of the Zolertia-Z1 mote.

During the semiconductor evaluation of modern Power Management Integrated Circuit (PMIC) devices, high quality Zero-Insertion-Force (ZIF) sockets must be used in order to measure many semiconductor parts with a single dedicated hardware. The most critical part of socket is contact between the device terminal and PCB. There are couples of technology processes that can provide solid contact between the device and the rest of the circuit, but the most common technology uses so called Pogo-pin, also called spring pin. Pogo pin must have as small as possible parasitic impedance, since the signal frequency and the signal power transfer between the PMIC terminal and the rest of the circuit must be without distortions, in order to obtain correct measurement results of tested devices. In some cases, influence of Pogo-pin parasitic impedance can lead to the partial damage of the device internal structure. This article should point to the potential problems using simulation results and should describe the simple procedure of Pogo-pin impedance characterization using network analyzer with appropriate aperture. Couples of measurements results from different Pogo-pin suppliers are also shown in this example with some practical results.

Input-output (I/O) cells in integrated circuit devices (ICs) are pushing data-rates to speeds of 5 Gb/s and above with an ever increasing number of pins. This is creating significant challenges for the automated test equipment (ATE) industry to develop appropriate interfaces that provide the needed performance. This article discusses crosstalk issues in high density, high performance ATE interconnects which usually include pogo pin type interfaces, mixed-dielectric printed circuit board (PCB) stack-ups with long differential traces, and innovative pogo/PCB via geometries. To demonstrate the crosstalk challenge and how to address it, a pogo pin assembly and pogo via design is analyzed as an example. This practical approach addresses aspects of creating the high performance interconnect such as pogo and PCB design issues, EM modeling, and measurements.

The root causes of the mechanical limitations are analyzed and their damages to the device-under-test (DUT) lead are demonstrated in this study. The evolution of microelectronics toward more densely packed contacts in a much smaller foot print has set a higher standard for the test socket used in the final test. This trend of evolution has brought several mechanical challenges for the pogo pin test socket, such as, (a) inability to overcome the trade off of the witness marks and contact resistance, (b) difficulties to target a specific contact area on a solder ball/unit leads when the pitches become too fine (c) difficulties in tolerance control as the pitch drops below 1.016 mm and (d) smaller metal contacts have lower fatigue life. All such problems are discussed here based on some experimental observations.

I/O cells operating up to 10 Gb/s, are now becoming standard blocks in complex integrated circuits (ICs). Integration of these multiple I/O cells in conjunction with other cores (e.g. mixed-signal) and higher power requirements has increased the pin count for some devices to above one thousand pins. This presents tough challenges for the automated test equipment (ATE) industry, in terms of developing solutions to address the data rate and routing density. This paper demonstrates a novel approach for designing a high density pogo pin transition to a multilayer planar PCB structure that achieves not only the required 10 Gb/s performance but also maintains the necessary density, and cost requirements that are inherent to an ATE solution.