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Recent developments in new switching methods, such as spin transfer torque and temperature-assisted switching (TAS), have greatly increased interest in MRAM. However, MRAM fabrication is challenging due to the lack of magnetic materials processing experience by semiconductor lines. In this talk, we will discuss key BEOL fabrication aspects for a CMOS-integrated TAS MRAM on 200 mm wafers with, e.g., opens/shorts yields of 100% and 99% for 1 Mb and 16 Mb arrays, resp. This was achieved in our R&D line through careful process optimization and adherence to good BEOL processing.

To achieve low write current in high density Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) arrays, it is important to understand and co-optimize the different kinds of device switching currents, governed by different materials parameters. We demonstrate that double magnetic tunnel junctions (DMTJs) lower the switching current threshold I c0 by a factor of two when compared to conventional single MTJs. In single MTJs, the overdrive required to reach a write-error rate (WER) of 1E-6 was reduced by materials optimization from 53% to 29% a write-error rate (WER) of 1E-6 by materials optimization. Ultra-low switching current of 8 µA at WER = 1E-9 was achieved in an 11 nm MTJ with 10 ns write pulses.

After some early successes with electroless Cu for printed circuit board wiring (1), and the use of electroless Co-based magnetic films over non-magnetic electroless nickel films on rigid Al disks in the magnetic storage industry, for several years, electroless deposition was never far from researchers’ interest in the field of microelectronics. This was in part due to the hope that it might replace some of the expensive vacuum metallization methods with less expensive and selective, or self-aligned, deposition methods. Electrolytic Cu deposition won out over electroless Cu deposition for CMOS BEOL (back-end-of-line) interconnect applications for a variety of reasons, including superior filling characteristics, conductivity, electromigration resistance, solution additives, relatively more stable solutions, absence of co-evolution of H2 gas, and higher deposition rates. A decade or more ago, it looked as if it electroless Co(W)(P) (2) was the ideal candidate to replace PVD Ta-based liners for CMOS BEOL builds, but despite meeting selectivity, diffusion barrier and reliability requirements, it was discarded, in part for cost reasons. In addition to the subtlety of its mechanisms and range of solution formulations, electroless deposition has much to offer in terms of niche applications, which explains why it is often turned to first by researchers seeking creative deposition methods in the still emerging field of nanofabrication. Examples pertinent to both “mainstream” and exploratory uses of electroless deposition will be discussed in this talk, including: capping layers to prevent interconnect Cu oxidation; diffusion barriers, and novel uses in nanofabrication. However, a brief discussion of the strong and weak points of electroless deposition in the context of use in nano/microfabrication will first be undertaken. While electroless deposition is capable of depositing only a limited number of metals and alloys compared to electrodeposition, materials with unique properties, such as Ni(P) (corrosion resistance) and Co(P) (magnetic properties), are readily obtained by electroless deposition. It is in principle easier to obtain coatings of uniform thickness and composition using the electroless process, since one does not have the current density uniformity problem of electrodeposition. Most electroless solutions operate in a mode approximating kinetic control. Strongly-adsorbing solution stabilizers, usually present in ppm-type concentrations, tend to decrease the deposition rate, though the classic, environmentally-unfriendly stabilizers like Pb2+ have been largely phased out. Rates will be lower for features smaller than the stabilizer diffusion layer thickness, while the edges of features, which experience higher stabilizer levels due to enhanced nonplanar diffusion, may experience reduced deposition rates, or may remain uncoated in extreme cases. To compound this problem, dissolved O2 gas effects the mixed potential of the surface being coated in the electroless solution since it is capable of being reduced; since the dissolved O2 is present in low concentration, similar nonplanar diffusion effects on coverage uniformity are observed. The presence of solution stabilizers and dissolved O2 may impart a practical lower limit to feature size that can be reproducibly fabricated using electroless deposition; solution agitation will play a major role in determining this practical feature size limit. We recently developed a maskless, electroless, high-P-content, Ni(P) process to protect the final Cu bitline wiring level in our STTM MRAM test vehicle to enable functional testing in an air atmosphere at elevated temperatures for evaluation of MRAM device memory state retention. The process was developed as a replacement for the final Al level, and had a drastically shorter process time. We demonstrated an electroless Ni(P) that selectively deposited on Cu bit lines with effective spacing approaching 200 nm without shorting, for coating thicknesses up to ca. 50 nm, with excellent bitline coverage (few pinholes). This was achieved through optimization of Cu surface cleanliness using a wet clean solution, followed by surface catalyzation using an acidic Pd solution, and finally immersion in the electroless Ni(P) solution for a fixed time. Testing (R & MR type) of Ni(P)-coated wafers, showed virtually unchanged resistance and MR for MRAM 4Kb arrays encompassing a large range of device critical dimensions (CDs). Figure 1 shows a topdown SEM image of a region of electroless Ni(P)-coated Cu bitlines. [1]. Please refer to papers in IBM J. Res. Develop., Vol. 28, Issue 6, year 1984, available online. [2]. See, e.g., Y. Shacham-Diamand, Y. Sverdlov and N. Petrov, J. Electrochem. Soc., 148(3) (2001) C162. Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out. Figure 1

Spin-torque Magnetoresistive Random Access Memory (ST-MRAM) is the subject of intense investigation since it extends MRAM technology to densities beyond those achieved with the earlier field-switched MRAM technology. This paper reviews recent developments in ST-MRAM MTJ device technology, including exciting progress in scaling MTJs down to dimensions approaching 20 nm. Fabrication issues relevant to development of ST-MRAM, including its integration with CMOS back-end-of-line (BEOL) processing, are also briefly discussed.

Spin-transfer torque [1] MRAM (STT-MRAM) continues to be the subject of intense investigation due to its scalability and excellent endurance. Initially explored mainly as a DRAM replacement, STT-MRAM with perpendicularly magnetized materials is now targeted as a nonvolatile memory, medium-performance replacement for mobile applications, and more long term as a fast, dense, cache memory. This talk will review MRAM magnetic stack etching methods and related aspects of integration, with particular reference to STT-MRAM. An STT-MRAM memory cell, which consists of a magnetic tunnel junction (MTJ) and a transistor, has the attractive property that if the critical current density for spin-torque switching (Jc) remains constant, then the critical current for MTJ switching (Ic) will scale as λ2, where λ is MTJ diameter . Thus, scaling is highly desirable for STT-MRAM. A significant research effort is also being devoted to developing MTJs with perpendicular magnetic anisotropy (PMA) materials [2] to achieve acceptably low switching currents, e.g., < 25 uA. Scaling is not without challenges, however, and the STT-MTJ arrays must, e.g., exhibit sufficient statistical margins between reading and writing operations, and must satisfy other key design properties including, a) sufficient TMR for the read signal, and b) a high enough energy barrier for up to 10 years of data retention. It has been found that fabrication processes like MTJ etching play key roles in MTJ performance to realize the full potential of newly-developed PMA materials, e.g., the ability to approach the resistance-area product RA measured by current-in-plane tunneling (CIPT) [3] on unprocessed MRAM stacks. The semiconductor industry seems to be preparing for large-scale manufacturing of STT-MRAM, by converging on an IBE-centered etching approach, followed by in situencapsulation. Minimizing metallic redeposition on the edge of the tunnel barrier during etching, and of edge-related magnetic damage, are key challenges in STTM patterning using IBE. Ohsawa et al. [4] showed that a typical MRAM IBE etching energy, e.g., 200 eV, causes a damage layer several monolayers thick at the patterned surface, suggesting that lower beam energies would be necessary during etching, or at least in the final damage-removal step. Confirming the promise of IBE, Samsung researchers Song et al. [5] recently reported high yields for an embedded STT-MRAM, patterned using IBE, with 8-Mbit density and a cell size of 0.0364 sq. micron. At IBM, following conventional 193 nm lithography, we have typically employed a RIE etch to pattern a Ta-based MTJ hardmask, stopping on a protective cap layer, which is then followed by MRAM stack etching using a combination of a MeOH-based RIE and IBE. Using arrays of different lithographically-printed MTJ mask diameters, final etched device sizes ranging from a high of about 100 nm down to 10 nm or less are typically obtained, as confirmed by TEM [6, 7]. Using this patterning approach, we demonstrated good STT performance down to 10-6 write-error-rate (WER) in a wide range of device sizes from 50 nm to 11 nm for a specific PMA STT-MRAM stack, for a statistically relevant sample of more than 650 devices [7]. We further demonstrated an individual 11 nm device switching down to WER = 7*10-10at 10 ns using only 7.5 uA current. [1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996). [2] For ex., D. C. Worledge et al., IEDM Tech. Dig., 296 (2010); S. Ikeda et al., Nature Mater., 9, 721 (2010). [3] D. C. Worledge and P. L. Trouilloud, Appl. Phys. Lett., 83, 84 (2003). [4] Y. Ohsawa et al., IEEE Trans. Magn., 52, 1 (2016). [5] Y.J. Song et al., IEDM, paper 27.2, (2016). [6] M. Gajek et al., Appl. Phys. Lett., 100, 132408 (2012). [7] J. J. Nowak et al., IEEE Magn. Lett., 7, 1 (2016). Acknowledgements We wish to thank E. Galligan, for technical support. The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where the magnetic device layers were fabricated.

We report switching performance of perpendicularly magnetized Spin-Transfer Torque MRAM (STT-MRAM) devices with double tunnel barriers and two reference layers. We show that stacks with double tunnel barriers improve the switching efficiency (Eb/Ic0) by 2x, when compared to similar stacks with a single tunnel barrier. Switching efficiency up to 10 kBT/uA was observed in single devices. A large operating window, Vbreakdown-Vc10ns ∼ 0.7 V was achieved for 40nm devices, compared to 0.2V in single tunnel barrier devices.

Spin Transfer Torque Magnetic Random Access Memory (MRAM) possesses a unique combination of high speed, high endurance, non-volatility, and small cell size. Among the emerging new memory technologies, including phase change memory, resistive random access memory, and conductive bridging random access memory, Spin Transfer Torque MRAM is the only candidate with the potential for unlimited endurance, since no atoms are moved during writing. This makes it the only potential candidate to replace dynamic random access memory (DRAM), when DRAM scaling comes to an end. DRAM is the ubiquitous working memory found in large quantities in nearly all computing systems. As DRAM is scaled below the 20 nm node, the capacitor on which the charge is stored needs to be made ever-taller, in order to maintain enough capacitance to store sufficient charge until the next refresh cycle. In addition to introducing significant process integration challenges, this also results in shorter charge storage time at advanced nodes, thus increasing the rate at which the DRAM needs to be refreshed. For a 64 Gb DRAM, it is predicted that the capacitor will leak so much that more than 40% of the time and almost half of the DRAM power will be spent on refreshing.[1] If the switching current for Spin Transfer Torque MRAM can be reduced below 10 uA, Spin Transfer Torque MRAM could replace DRAM below the 20 nm node. Write current largely determines the cost of Spin Transfer Torque MRAM, since the transistor and hence cell area must be sized large enough to source the write current. It is important to distinguish between several related switching currents. Physicists often speak of the switching current threshold, Ic0. The switching current is measured with slow pulses and extrapolated back to 1 ns. Theoretically, Ic0 corresponds to the switching threshold at zero temperature. A more technologically relevant parameter is Ic10ns, the array-average switching current for a 10 ns pulse. Since these measurements are usually single-shot measurements, this corresponds to a switching probability of about 0.5. However, this is not the write current, Iwrite, for which the transistor needs to be sized, since it does not take into account the additional current required to obtain reliable writing or the bit-to-bit distribution in switching current. For a 1-bit error correction code, a typical requirement for the probability of not switching is Pns = 1e-12 (this depends slightly on the size of the memory, the retention requirement, and the bit-to-bit distribution of activation energy). Measured data showed that the switching voltage increased from ∼ 0.35 V to ∼ 0.5 V in order to decrease the probability of not switching from Pns = 0.5 to Pns = 1e-12.[2] Furthermore, measurements on 500 junctions gave a standard deviation of about 4.5% of the mean switching voltage.[3] Keeping in mind that the above data was measured on large ∼ 100 nm junctions, we can use this data to make a rough estimate of Iwrite = (0.5/0.35)(1+6∗4.5%)Ic10ns, which takes into account writing 6 sigma junctions from a Gaussian distribution. Hence we can expect Iwrite to be roughly twice Ic10ns. If a minimum feature size FinFet can source roughly 20 uA, then the requirement on switching current is Ic10ns < 10 uA.

The implementation of magnetic random access memory (MRAM) hinges on complex magnetic film stacks and several critical steps in back-end-of-line (BEOL) processing. Although intended for use in conjunction with silicon CMOS front-end device drivers, MRAM performance is not limited by CMOS technology. We report here on a novel test site design and an associated thin-film process integration scheme which permit relatively inexpensive, rapid characterization of the critical elements in MRAM device fabrication. The test site design incorporates circuitry consistent with the use of a large-area planar base electrode to enable a processing scheme with only two photomask levels. The thin-film process integration scheme is a modification of standard BEOL processing to accommodate temperature-sensitive magnetic tunnel junctions (MTJs) and poor-shear-strength magnetic film interfaces. Completed test site wafers are testable with high-speed probing techniques, permitting characterization of large numbers of MTJs for statistically significant analyses. The approach described in this paper provides an inexpensive means for rapidly iterating on MRAM development alternatives to converage on an implementation suitable for a production environment.

Magnetic random access memory (MRAM) technology, based on the use of magnetic tunnel junctions (MTJs), holds the promise of improving on the capabilities of existing charge-based memories by offering the combination of nonvolatility, speed, and density in a single technology. In this paper we review rapid-turnaround methods which have been developed or applied in new ways to characterize MRAM chips at various stages during processing, with particular emphasis on the MTJs. The methods include current-in-plane tunneling (CIPT), Kerr magnetometry, vibrating sample magnetometry (VSM), and conducting atomic force microscopy (CAFM). Use of the methods has enabled rapid learning with respect to the materials used for the MTJs, as well as tuning of the MTJ geometry in terms of size and shape and of the patterning methods employed. Examples of the use of each of the methods are presented along with interpretation of the data via critical operating parameters.

We demonstrate a method for measuring magnetoresistance (MR) and resistance area product (RA) of unpatterned magnetic tunnel junction film stacks. The RA is measured by making a series of four point probe resistance measurements on the surface of an unpatterned wafer at various probe spacings. The key to this technique is in placing the probes at the appropriate spacings, on the order of microns for typical applications. The MR is obtained by repeating the measurement at different magnetic fields. A simple conceptual model and an exact analytical solution in good agreement with experimental data are presented. The current-in-plane tunneling method requires no processing, is fast, and provides reliable data which are reflective of the deposition only.

The switching current of Spin Torque Magnetic Random Access Memory (MRAM) can be reduced significantly by using perpendicularly magnetized materials. The Ta|CoFeB|MgO system provides both high tunneling magnetoresistance and perpendicular anisotropy. Using this materials system we have demonstrated basic write functionality in fully integrated Spin Torque MRAM arrays. Here, we further demonstrate device scaling down to 20 nm diameter, opening up the possibility of ultra-dense Spin Torque MRAM.

Recently developed magnetic tunnel junctions with full perpendicular magnetization that are spin-torque switchable allow for quantitative comparison of spin-torque switching statistics with a macrospin model. For typical devices above 50 nm in lateral size, the comparison suggests the presence of subvolume magnetic excitations which often dominate the switching process and which degrade the spin-torque switching efficiency. A simple model of subvolume spin-torque-driven magnetic switching is presented to account for the experimental observations. The origin of the subvolume thermal excitation is traced to a competition between the macrospin fluctuation within a simple uniaxial anisotropy potential and that of thermal magnon excitation. The subvolume excitation problem highlights the importance of improving the magnetic exchange stiffness of the junction free layer, and the reduction of junction lateral sizes below 50 nm where an improved spin-torque efficiency is seen as the switching dynamics cross over to a more macrospin-like process.

PMA spin-torque switchable junctions have been demonstrated with lower switching current and faster switching speed compared to IMA devices. They are promising for further technology exploration in solid-state memory applications.

We report data from 4-kbit spin torque MRAM arrays using tunnel junctions (TJs) with magnetization perpendicular to the wafer plane. We show for the first time the switching distribution of perpendicular spin torque junctions. The percentage switching voltage width, σ(V c )/ = 4.4%, is sufficient to yield a 64 Mb chip. Furthermore we report switching probability curves down to error probabilities of 5×10−9 per pulse which do not show the anomalous switching seen in previous studies of in-plane magnetized bits.

Recent developments in new switching methods, such as spin transfer torque [1] and temperature-assisted switching (TAS) [2], have greatly increased interest in MRAM. MRAM fabrication is challenging, however, due to the lack of magnetic materials processing experience by semiconductor lines. In this talk, we will discuss key back-end-of-line (BEOL) fabrication aspects for a CMOS-integrated thermally-assisted (TAS) MRAM on 200 mm wafers with, e.g., opens/shorts yields of 100% and 99% for 1Mb and 16 Mb arrays, resp. The cell sizes were 33F^2 for the 16M cell, and 73F^2 for the 1M cell, where F = 90 nm. This was achieved in our Microelectronics Research Laboratory (MRL) facility through careful process optimization and adherence to good BEOL processing practice. Factors influencing opens and shorts yields will be discussed. In the TAS-MRAM magnetic tunnel junction (MTJ) device, data retention is enhanced through synthetic antiferromagnetic exchange coupling; during writing; coupling is overcome through passage of a heating current through the MTJ, and a lower switching field suffices to switch the heated device [2]. Figure 1 contains TEMs of a TAS MRAM structure with two dual-Damascene Cu levels and an Al level after the MTJ. The 90 nm base FEOL/BEOL CMOS technology wafers were fabricated by a third party. Fabrication at IBM commenced at V3, and trilayer via and trench RIE masking schemes were used below the final Al level. The field line (M4) had ferromagnetic (FM) cladding of either PVD Ni-Fe alloy or Co. Cladding proved challenging for narrow field lines (≤ 0.5 µm); e.g., in the initial stages of Cu plating, imperfect corner seedlayer coverage led to solution attack of the Co. A Damascene TaN layer (ca. 50 nm thick) served as the pedestal for the MTJ. The MTJ resist mask patterns were trimmed using RIE to afford, after MTJ methanol-based RIE etching, final device sizes of about 110 nm. After MTJ encapsulation with SiN and dielectric deposition, V4 vias were RIE etched, stopping on SiN. During M5 dielectric RIE, the MTJ pillar tops were exposed, and the V4 vias’ SiN cleared. The final V5/M6 Cu level was followed by an Al level. Besides the FM liner, other processing challenges included clearing isolated vias, and developing a robust trench RIE process to contact the MTJs. [1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996). [2] For example, I. L. Prejbeanu et al., J. Phys: Condens. Matter, 19 (16), 165218 (2007). Acknowledgements: Back-end-of-line fabrication was carried out in the Microelectronics Research Laboratory (MRL) at the T. J. Watson Research Center. The MRAM stacks were deposited at Crocus Technology in Grenoble, France. Figure 1

Magnetic materials are investigated in order to enable a new type of Thermally Assisted Magnetic Random Access Memory (TAS-MRAM). A TAS-MRAM materials stack that is robust against the 400 °C process temperatures required for embedded integration with complementary metal oxide silicon processes is demonstrated. In unpatterned sheet film stacks, a stable resistance-area product, tunneling magnetoresistance (MR) > 100%, and temperature-dependent exchange bias of 1500 Oe after 400 °C anneal are shown for this stack. It is further shown that by doping the sense and storage layers with Ta using thin laminations of Ta/CoFeB, the moment of each layer can be reduced by more than 40% without a major reduction in MR. In patterned nanopillar devices, it is shown that by reducing the moment of the sense and storage layers with laminations of Ta, and by adding a second MgO barrier, the resistance versus applied field loop quality is maintained, while the read field is reduced by more than 40% and devices survive 108 wr...

MRAM technology offers an attractive combination of performance, density, low power, non-volatility, and write endurance. While first stand-alone MRAM products appear poised for introduction, major technology advances are also being reported. In this review, we discuss our work on a 16Mbit demonstrator chip with a 1.42 /spl mu/m/sup 2/ cell in 180 nm technology in the context of recent world wide advances in MRAM technology. These include a cell architecture that resolves the magnetic half select write disturb issue and an advanced tunnel barrier material, MgO, that promises much larger signals for MRAM read operations.

Small magnetic tunnel junctions were prepared and the magnetization reversal of their free layers was studied by applying high-speed reversal fields driven by pulsed currents. From the decay of the switching field with the number of pulses or the pulse length the thermal activation energy was deduced. Large cells (width>150 nm) showed a significant lower activation energy than expected from single-domain-theory, indicating non-uniform switching. Small cells (width /spl sim/ 90 nm and length 150 to 200 nm) could be well described by Stoner-Wohlfarth single domain model and single step switching with Arrhenius activation energy. For scaling of magnetic random access memories down to 100 nm this would indicate that a smaller free layer volume is to a large degree compensated by higher relative activation energy due to more uniform switching.

The discovery of perpendicular magnetic anisotropy (PMA) in Ta|CoFeB|MgO and the subsequent development of perpendicularly magnetized tunnel junctions at IBM is reviewed. The fast-turn-around method used for screening materials for interface PMA by measuring the moment/area and anisotropy field of in-plane materials as a function of CoFeB thickness is presented, including the data as a function of seed-layer material which led to the discovery of PMA in Ta|CoFeB|MgO. Magnetic and electrical data are reported for the first PMA magnetic tunnel junction we made using this material. By inserting a thin Fe layer at the Ta|CoFeB interface, a substantial increase in the PMA energy density was obtained. Pure Fe layers (which required the use of a TaMg seed) greatly improved the thermal stability, allowing annealing up to 400 °C.

not Available.

CoFeB-based magnetic tunnel junctions with perpendicular magnetic anisotropy are used as a model system for studies of size dependence in spin-torque–induced magnetic switching. For integrated solid-state memory applications, it is important to understand the magnetic and electrical characteristics of these magnetic tunnel junctions as they scale with tunnel junction size. Size-dependent magnetic anisotropy energy, switching voltage, apparent damping, and anisotropy field are systematically compared for devices with different materials and fabrication treatments. Results reveal the presence of sub-volume thermal fluctuation and reversal, with a characteristic length-scale of the order of approximately 40 nm, depending on the strength of the perpendicular magnetic anisotropy and exchange stiffness. To have the best spin-torque switching efficiency and best stability against thermal activation, it is desirable to optimize the perpendicular anisotropy strength with the junction size for intended use. It also is important to ensure strong exchange-stiffness across the magnetic thin film. These combine to give an exchange length that is comparable or larger than the lateral device size for efficient spin-torque switching.

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising emerging non-volatile memory technologies. MRAM has so far been demonstrated with a unique combination of density, speed, and non-volatility in a single chip, however, without the capability to replace any single mainstream memory. In this paper, we demonstrate the basic physics of spin torque switching in 20 nm diameter magnetic tunnel junctions with perpendicular magnetic anisotropy materials. This deep scaling capability clearly indicates the STT MRAM device itself may be suitable for integration at much higher densities than previously proven.

Spin torque switching is investigated in perpendicular magnetic tunnel junctions using Ta∣CoFeB∣MgO free layers and a synthetic antiferromagnet reference layer. We show that the Ta∣CoFeB interface makes a key contribution to the perpendicular anisotropy. The quasistatic phase diagram for switching under applied field and voltage is reported. Low switching voltages, Vc 50 ns=290 mV are obtained, in the range required for spin torque magnetic random access memory. Switching down to 1 ns is reported, with a rise in switching speed from increased overdrive that is eight times greater than for comparable in-plane devices, consistent with expectations from a single-domain model.

Bit error rates below 10-11 are reported for a 4-kb magnetic random access memory chip, which utilizes spin transfer torque writing on magnetic tunnel junctions with perpendicular magnetic anisotropy. Tests were performed at wafer level, and error-free operation was achieved with 10 ns write pulses for all nondefective bits during a 66-h test. Yield in the 4-kb array was limited to 99% by the presence of defective cells. Test results for both a 4-kb array and individual devices are consistent and predict practically error-free operation at room temperature.

A three-terminal spin-torque-driven magnetic switch is experimentally demonstrated. The device uses nonlocal spin current and spin accumulation as the main mechanism for current-driven magnetic switching. It separates the current-induced write operation from that of a magnetic tunnel junction based read. The write current only passes through metallic structures, improving device reliability. The device structure makes efficient use of lithography capabilities, important for robust process integration.

For CoFeB∕MgO-based magnetic tunnel junctions, the switching probability has an unusual dependence on bias voltage V and bias magnetic field H for bias voltage pulse durations t long enough to allow thermally activated reversal. At high junction bias close to 1V, the probability of magnetic switching in spin-torque-driven switches sometimes appears to decrease. This is shown to be due to a backhopping behavior occurring at high bias, and it is asymmetric in bias voltage, being more pronounced in the bias direction for antiparallel-to-parallel spin-torque switch, i.e., in the direction of electrons tunneling into the free layer. This asymmetry hints at processes involving hot electrons within the free-layer nanomagnet.

We present room-temperature measurements of high-frequency magnetization fluctuation (mag noise) in MgO-based nanopillar magnetic tunnel junctions (MTJs) biased with a direct current (dc). In the frequency range of 1–13 GHz, double mag-noise peaks are observed for some MTJs while others only show a single mag-noise peak. The in-plane field dependence of the mag-noise peak frequency is consistent with the Kittel formula. For all MTJs measured, the bias-dependent shift in the mag-noise peak frequency has a pronounced asymmetry. In addition, we find nonmonotonic variations in peak linewidth as a function of the external in-plane magnetic field and of the dc bias current. These suggest the possible involvement of nonmacrospin modes in spin-torque-dependent thermal mag-noise generation.

The authors analyze the critical switching curve for two identical coupled magnetic free layers, as used in toggle magnetic random access memory. The continuous and discontinuous transitions between different magnetic states are described. A general criteria for toggling is derived by summing up the number of clockwise and counterclockwise transitions, leading to a larger toggle region than previously reported. It also leads to a significant chirality effect, wherein the toggle region shifts depending on the order in which the word and bit line fields are applied. Finally, the authors discuss a type of switching useful for experimentally measuring the critical switching curve.

Toggle magnetic random access memory (MRAM) has been proposed to solve the problems of small switching margins and half-select activated errors found in Stoner-Wohlfarth MRAM. However, it is widely acknowledged that the switching fields required for toggle MRAM are substantially larger than those needed for Stoner-Wohlfarth MRAM. Previously published reports on toggle switching use large toggle start fields around 75Oe. Here we examine, both experimentally and with a single-domain model, how both the toggle start and end fields vary with free layer intrinsic anisotropy, thickness, width, aspect ratio, and interlayer exchange coupling. By optimizing these parameters, we obtain 400nm width devices with toggle start fields below 30Oe.

Magnetoresistance measurements can be used during manufacturing to characterize basic magnetic parameters at the device level. A fruitful approach is to take advantage of the gradient field generated by the current flowing through the sample. This method was employed by Smith et al. in an elegant series of experiments that led to precise measurements of exchange constant in soft magnetic thin films. In the present paper, local coupling in bilayers, anisotropy, and interface quality are investigated using magnetoresistive response to gradient fields. Permalloy samples consisting of two sputtered layers (0.1 μm thick) separated by thin SiO2 spacers were patterned in the form of long stripes parallel to the easy axis. Variation in resistance was measured as a function of external field applied in the easy‐axis direction and of current density. For similar geometries, the samples have similar resistance. The curves display a sharp decrease in the resistance near zero field that is associated with the reversal...