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Autonomous systems require high-performance processing capabilities, which demand the use of powerful accelerators such as GPUs. However, the use of GPUs in critical systems presents several challenges, since GPU programming models rely on explicit dynamic memory management. Traditionally, dynamic memory allocation in such systems is restricted to certain controlled scenarios, which require programs to be rewritten so that all the required memory is allocated at the beginning of the program and released at its end. However, many GPU applications do not follow this approach. Moreover, when dynamic memory allocation is used, it is critical to compute the exact amount of memory that will be used as well as to minimize it, to guarantee that it fits in the physical system memory. In this paper we present XeroZerox, an open-source tool that automatically converts the traditional dynamic memory allocations of GPU applications into allocations served from a centralized and optimally sized memory pool, which is managed in a way better suited for critical systems. XeroZerox allows legacy GPU applications to be used in a critical setup without rewriting them, minimizing at the same time their memory consumption and memory management runtime overhead., European Union’s Horizon Europe Program through the Modular Model-Based Design and Testing for Applications in Satellites (METASAT) (Grant Number: 101082622) Spanish Ministry of Economy and Competitiveness (Spanish State Research Agency/Agencia Española de Investigación (Grant Number: PID2019-107255GB-C21 and IJC-2020-045931-I) Department of Research and Universities of the Government of Catalonia with a Grant to the Computer Architecture and Operating Systems (CAOS) Research Group (Grant Number: 2021 SGR 00637), Peer Reviewed, Postprint (published version)

Multicore architectures are currently under adoption in the aerospace domain, however their software remains single-threaded. In this paper we argue about the benefits offered by homogeneous parallel processing, both in terms of performance, which is necessary for the implementation of advanced functionalities, as well as in terms of certification and in particular about mastering multicore interference.We discuss the implementation details of this programming paradigm in avionics and space real-time operating systems. We experimentally evaluate the performance benefits offered by several high-performance multicore platforms which are considered good candidates for next generation flight computers, using homogeneous parallel processing under a qualifiable real-time operating system used in the aerospace domain. Our results indicate near to linear speed-ups compared to traditional sequential processing, showing the benefits of this approach., This work was supported by the European Union’s Horizon Europe programme under the METASAT project (grant agreement 101082622). In addition, it was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) ESAfunded project. It was also partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC-2020-045931-I ( Spanish State Research Agency / Agencia Española de Investigación (AEI) / http://dx.doi.org/10.13039/501100011033 ) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637)., Peer Reviewed, Postprint (author's final draft)

The space domain, as many other sectors, is actively considering novel methods and tools based on artificial intelligence, digital twins, virtual design and testing, and other Industry 4.0 concepts, in order to manage the increased complexity of the design of upcoming satellites. Nevertheless, especially from the satellite on-board software engineering point of view, these technologies require a solid ground to be built upon. First of all, the computational power of the hardware platform must meet the needs of the advanced algorithms running on top of it. The software layer too must both allow an efficient use of the hardware resources and at the same time guarantee non-functional properties such as dependability in compliance with ECSS standards. Finally, the design methods need to adapt to the specific challenges posed by both the increased complexity of the hardware/software and Industry 4.0. The METASAT Horizon Europe Project which started in January 2023 will address these challenges. The METASAT vision is that a design methodology based on model-based engineering jointly with the use of open architecture hardware constitutes that solid ground. To reach its vision, METASAT will leverage existing software virtualisation layers (e.g., hypervisors), that already provide guarantees in terms of standards compliance, on top of high-performance computing platforms based on open hardware architectures. The focus of the project will be on the development of a toolchain to design software modules for this hardware/software layer. Without such measures, the time and cost of developing new systems could become prohibitive as system complexity grows, reducing competitiveness, innovation, and potentially dependability across the industry., The research presented throughout this paper has received funding from the European Commission’s Horizon Europe programme under the METASAT project (grant agreement 101082622)., Peer Reviewed, Article signat per 20 autors/es: Leonidas Kosmidis1; Alejandro J. Calderón2; Aridane Álvarez Suárez3; Stefano Sinisi4; Eckart Göhler5; Paco Gómez Molinero3; Alfred Hönle5; Alvaro Jover Alvarez1; Lorenzo Lazzara4; Miguel Masmano Tello3; Peio Onaindia2; Tomaso Poggi6; Iván Rodríguez Ferrández1; Marc Solé Bonet1; Giulia Stazi4; Matina Maria Trompouki1; Alessandro Ulisse4; Valerio Di Valerio4; Jannis Wolf1, and Irune Yarza2 / 1 Barcelona Supercomputing Center (BSC), Barcelona, Spain; 2 Ikerlan Technology Research Centre, Arrasate-Mondragón, Spain; 3 FENT Innovative Software Solutions, Valencia, Spain; 4 Collins Aerospace - Applied Research and Technology, Rome, Italy; 5 OHB System AG, Bremen, Germany; 6 Mondragon Unibertsitatea, Arrasate-Mondragón, Spain., Postprint (author's final draft)

The rise in complexity of the algorithms run on space systems, largely attributable to higher resolution instruments which generate a large amount of the data to be processed, as well as to the need for increased autonomy which relies on Neural Network inference systems in future missions, demand the adoption of more powerful on-board hardware, such as multicores. At the same time, the correctness and reliability of critical on-board software is of paramount importance for the success of the missions. However, developing such complex software in low-level languages can have a negative impact on these aspects. For this reason, this thesis evaluates the role that the Rust programming language can have in this change, given its memory safety and built in support for parallelism, which allows to better utilise more powerful hardware, in particular multicore cpus, without compromising programmability and safety of the code. To this end, the GPU4S benchmarking suite, part of the open source OBPMark benchmarking suite of the European Space Agency (ESA), is ported to Rust, with sequential and parallel implementations. The applications are ported both in a hosted as well as in bare metal environment for a RISC-V based platform for the space domain, developed within the METASAT Horizon Europe project. The performance of the ported benchmarks is compared to the existing sequential and parallel implementations in low-level languages to evaluate the trade-offs of the different solutions, and it is evaluated on several multicore platforms which are candidates for future on-board processing systems. A particular focus is put on parallel versions of the benchmarks, where Rust offers solid native support, as well as library support for fast parallelization similar to OpenMP. Finally, in terms of correctness, the Rust implementations are free of recently detected defects in the low-level implementations of the GPU4S benchmarks.

Critical Real-Time Embedded Systems (CRTES) are aimed to be executed on Real Time processors under time constraints. To ensure the correct execution under these constraints, a Worst Case Execution Time (WCET) analysis must be performed in every CRTES developing project. Conventional WCET analysis slows down CRTES development as it requires a lot of economic and time resources, and also takes into consideration only the worst case value without taking into account the probability to achieve it. Instead, Measurement Based Probabilistic Timing Analysis (MBPTA) provides a probabilistic Worst Case Execution Time (pWCET) curve. TASA was born as a solution to realize MBPTA, using a flexible and portable code-randomization tool. In this work the TASA tool-chain has been developed and its functionalities are being explained, alongside with a demonstration of its correctness, compiling and executing a real time project and realizing a MBPTA of itself.

Recent trends in Data Handling Systems (DHS) include increased data-rates, in-orbit reconfiguration and the introduction of advanced On-Board Processing (OBP) methods to extract actionable information on-board, with low latency. At the same time, NewSpace industry has successfully deployed COTS-based DHS and processing equipment in space. In particular for OBP, COTS-based processors and FPGAs can offer higher computational performances than space qualified equivalents – which in turn can enable new applications through more advanced OBP algorithms. The individual component cost is also lower for COTS than space qualified components, which can allow overall cost-optimisations on mission level.An internal working group at ESA has studied the concept of using "safety barriers" to ensure no propagation of failure from functions implemented with COTS to other on-board units. Thanks to ESA studies there is a path to use Class IV equipment on missions with higher class (Class I-III), through the use of hardware "safety barriers" to limit failure propagation from Commercial Off-The-Shelf (COTS) equipment.In our work, we take the above mentioned concepts and apply them to reference implementations, targeting payload processing modules based on standard form factors (ADHA) and automotive-grade GPU Systems-on-Chip (SoCs). In addition, we make use of previous work on improving in-flight availability of complex COTS SoC processors, through system and software Fault Detection, Isolation and Recovery (FDIR) techniques., This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) ESA-funded project. Moreover, it was supported by the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622). In addition, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GBC21 and IJC-2020-045931-I ( Spanish State Research Agency / Agencia Espanola de Investigacion (AEI) / http://dx.doi.org/10.13039/501100011033 ) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637). Leonidas Kosmidis was partially supported by the Spanish Ministry of Economy and Competitiveness under grant IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033)., Peer Reviewed, Postprint (author's final draft)

On-board Image Processing is one of the most computationally intensive tasks performed in space payload processing. With the constant increase in the resolution of optical sensors, new powerful architectures are needed for their processing. In this work, we evaluate the capabilities of several state-of-the-art embedded COTS and radiation tolerant multicore and GPU featuring platforms, with an open source on-board image processing application we have developed and parallelised. Our results show that both embedded multicores and especially GPUs are very effective for such tasks. In fact, GPUs become even more efficient when sensor sizes are increasing, making them ideal candidates for future space missions., This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) ESA-funded project. Moreover, it was supported by the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No. 772773) and European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622). In addition, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC-2020-045931-I (Spanish State Research Agency / Agencia Espanola de Investigacion (AEI) / http://dx.doi.org/10.13039/501100011033) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637)., Peer Reviewed, Postprint (author's final draft)

The METASAT Horizon Europe project which is funded by the European Commission and started in January 2023, will enable model-based design methodologies in order to manage the complexity of upcoming hardware and software for space on-board processing. As a representative high performance platform for on-board processing, METASAT will design a multi-core platform featuring accelerators prototyped on an FPGA. This includes both an AI SIMD accelerator tightly integrated with the CPU, as well as a GPU. All hardware components of the METASAT platform will be open source and based on the RISC-V open ISA. In this paper, we provide an overview of the platform architecture as well as preliminary implementation decisions, current development status and early results., This work was supported by the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622). In addition, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GBC21 and IJC-2020-045931-I ( Spanish State Research Agency / Agencia Espanola de Investigacion (AEI) / http://dx.doi.org/10.13039/501100011033 ) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637)., Peer Reviewed, Postprint (author's final draft)

El acelerador SPARROW AI portátil y de bajo costo se propuso y demostró recientemente en VHDL en dos procesadores espaciales, el LEON3 y el NOEL-V. En este trabajo de fin de grado se implementa SPARROW en SystemVerilog y se integra con un procesador RISC-V escrito en SystemVerilog, el SweRV Core EH1. Esta implementación proporciona tres resultados importantes. Demuestra la portabilidad de SPARROW, proporciona una extensión útil a un procesador de grado industrial existente y nos brinda la capacidad de comparar las implementaciones de SPARC y RISC-V. Los resultados obtenidos demuestran que SPARROW puede proporcionar aceleraciones significativas también en el núcleo EH1 de doble emisión., The low-cost and portable SPARROW AI accelerator has been recently proposed and demonstrated in VHDL in two space processors, the LEON3 and NOEL-V. In this Bachelor's thesis, SPARROW is implemented in SystemVerilog and is integrated with a RISC-V processor written in SystemVerilog, the SweRV Core EH1. This implementation provides three important results. It proves the portability of SPARROW, provides a useful extension to an existing industrial grade processor, and give us the ability to compare the SPARC and RISC-V implementations. The obtained results demonstrate that SPARROW can provide significant speedups also in the dual issue EH1 core.

Worst Case Execution Time estimation of software running on parallel platforms is a challenging task, due to resource interference of other tasks and the complexity of the underlying CPU and GPU hardware architectures. Similarly, the increased complexity of the hardware, challenges the estimation of worst case power consumption. In this paper, we employ Measurement Based Probabilistic Timing Analysis (MBPTA), which is capable of managing complex architectures such as multicores. We enable its use by software randomisation, which we show for the first time that is also possible on GPUs. We demonstrate our method on a pedestrian detection use case on an embedded multicore and GPU platform for the automotive domain, the NVIDIA Xavier. Moreover, we extend our measurement based probabilistic method in order to predict the worst case power consumption of the software on the same platform., This work was funded by the Ministerio de Ciencia e Innovación - Agencia Estatal de Investigación (PID2019-107255GB- C21/AEI/10.13039/501100011033 and IJC-2020-045931-I), the European Commission’s Horizon 2020 programme under the UP2DATE project (grant agreement 871465), an ERC grant (No. 772773) and the HiPEAC Network of Excellence, Peer Reviewed, Postprint (author's final draft)

Upcoming safety critical systems require high performance processing, which can be provided by multi-cores and embedded GPUs found in several Systems-on-chip (SoC) targeting these domains. So far, only low-level programming models and APIs, such as CUDA or OpenCL have been evaluated. In this paper, we evaluate the effectiveness of a higher level programming model, SYCL, for critical applications executed in such embedded platforms. In particular, we are interested in two aspects: performance and programmability. In order to conduct our study, we use the open source GPU4S Bench benchmarking suite for space and an open source pedestrian detection application representing the automotive sector, which we port into SYCL and analyse their behavior. We perform our evaluation on a high-performance platform featuring an NVIDIA GTX 1080Ti as well as a representative embedded platform, the NVIDIA Xavier AGX which is considered a good candidate for future safety critical systems in both domains and we compare our results with other programming models. Our results show that in several cases SYCL is able to obtain performance close to highly optimised code using CUDA or NVIDIA libraries, with significantly lower development effort and complexity, which confirms the suitability of SYCL for programming high-performance safety critical systems., This work was funded by the Ministerio de Ciencia e Innovacion - Agencia Estatal de Investigacion (PID2019-107255GB-C21 and IJC-2020-045931-I MCIN/AEI/10.13039/501100011033), the European Commission’s Horizon 2020 programme under the UP2DATE project (grant agreement 871465) and the HiPEAC Network of Excellence., Peer Reviewed, Postprint (author's final draft)

(English) Future Safety-Critical Systems require a boost in guaranteed performance in order to satisfy the increasing performance demands of the state-of-the-art complex software features. Ar1 approach to achieve these performance requirements is the usage of High-Performance Computing (HPC) components which can deliver more computation power than current safety­ critical components. However, the dependability support of these HPC components are not the same as that for the safety-­ critical components, so HPC components can jeopardize the functional safety of the entire system, especially since some of the highest-criticality functionalities maybe executed entirely on top of these components (e.g., neural networks in a Graphical Processing Unit (GPU)). Based on the safety requirements of performance-hungry critical applications, such as those for an autonomous operation, these HPC components must comply with the highest criticality levels, hence including the required dependability support. The overarching goal of this thesis is to present techniques to achieve that in different HPC components. In particular, we focus on GPUs and multicores. The techniques presented aim at providing diverse redundant execution, as needed to avoid Common Cause Failure (CCF)s, which are those defeating safety measures (e.g., pure redundancy) as a consequence of a single-point fault (e.g., a fault affecting both redundant instances identically). Such a solution is comparable to the lockstep execution employed on safety-critical processors. The first set of contributions of this thesis focuses on enabling diverse redundant execution on a single GPU. We propose two different solutions: (1) a slight hardware modification affecting the internal scheduler of the GPU and (2) a software-only approach that requires knowledge of the hardware resources of the GPU. In these contributions, we also analyze the staggering created due to the CPU-GPU inherent interaction. Finally, the last contributi, (Català) Els futurs sistemes de fiabilitat critica necessitaran un increment en el rendiment garantit per tal de salisfer l'elevada demanda de computaci6 del complex programari que actualment es l'estat de l'art. Una estrategia per aconseguir aquest rendiment es utilitzar components del camp de la computaci6 d'altes prestacions (HPC), ja que poden aportar mes poder de computaci6 que els actuals components de fiabilitat critica. Tanmateix, el suport de fiabilitat que tenen aquests HPC components no es el mateix que tenen els components de fiabilitat crilica, i l'us dels components HPC pot amenar;:ar la seguretat funcional de tot el sistema, especialment si algunes de les funcionalitats d'alta criticalitat poden ser totalment executades en algun d'aquests components (perexemple, xarxes neuronals dins d'una unitatde computaci6 grafica (GPU)). Basant-se en els requisits de fiabilitat de les aplicacions que requereixen una gran potencia de computaci6, com les d'operaci6 aut6noma, aquests components d'altes prestacions han de complir els maxims nivells de fiabilitat i per tan incloure mecanismes que aportin aquesta fiabilitat. L'objectiu general d'aquesta tesi es presentar tecniques per aconseguir aquests nivells en component d'altes prestacions. En concret, fem enfasis en unitats de computaci6 grafiques i sistemes multinucli. Les tecniques presentades tenen la intenci6 de proveir una execuci6 redundant i diversa, la qual es necessita per evitar les fallades de causa comuna (CCF), que s6n el tipus de fallades de les quals no poden ser protegides utilitzant metodes de fiabilitat (com simple redundancia) i que tenen un unic punt de fallada (una fallada que afecti les dues instancies redundants identicament). Aquestes solucions s6n comparables a l'execuci6 en lockstep (pas de bloqueig) emprada en sistemes de fiabilitat critica. El primer grup de contribucions d'aquesta tesis es bas en a habilitar una execuci6 redundant i diversa en una sola unitat de computaci6 grafica. Prop, Postprint (published version)

Modern safety critical systems require high levels of performance for the implementation of advanced functionalities, which are not possible with the simple conventional architectures currently used in them. Embedded General Purpose Graphics Processing Units (GPGPUs) are among the hardware technologies which can provide the high performance required in these domains. However, their massively parallel nature complicates the verification of their software and increases its cost because it usually involves code coverage through extensive human-driven testing. The Ada-SPARK language has traditionally been used in highly-critical environments for its formal verification capabilities and powerful type system. The use of such tools, especially those being backed up by theorem provers, has significantly lowered the amount of effort needed to validate functionality of safety-critical systems. In this work, we utilize AdaCore's CUDA backend for Ada ---currently in closed beta--- in conjunction with the SPARK language subset to assess the state of static verification for GPU kernels. We show how common programming mistakes in GPU kernels can be prevented, formulate a pattern for buffer overflow detection, and close with a few GPU case studies.

Recently the ASIC industry experiences a massive change with more and more small and medium businesses entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector – which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs – if we can show that the produced chips have favourable radiation properties. In this paper, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors., This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments”. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622)., Peer Reviewed, Postprint (author's final draft)

In the past decade, Artificial Intelligence has revolutionized various industries, including automotive, avionics, and health sectors. The installation of Advanced Driver Assistance Systems (ADAS) is now a reality, with the goal of achieving fully self-driving cars (SDCs) in the near future. ADAS and Autonomous Driving (AD) systems require processing vast amounts of data at high frequency using complex algorithms (Deep Learning (DL)) to meet tight time constraints (Real Time (RT)). Traditional computing has become a bottleneck, with CPUs unable to handle the data efficiently. High-performance GPUs have partially fulfilled these timing constraints, leading to continuous innovation in device performance and efficiency. For example, Nvidia introduced the Jetson AGX Xavier SoC in 2017, designed for machine learning applications in the automotive sector. However, AD and ADAS challenges also involve safety constraints, such as functional safety. Redundancy is necessary for identifying and correcting erroneous outcomes. To ensure high safety levels, diverse redundancy is used to avoid common cause faults (CCF). High-performance hardware for AD must be verified and validated (V&V) to ensure safety goals, but these processes can be costly. The automotive industry seeks to avoid non-recurring costs by using commercial off-the-shelf products (COTS). However, COTS devices have drawbacks, including limited redundancy and guarded implementation details. Researchers are developing software-only diverse redundancy solutions on top of COTS devices to overcome these limitations. Two main challenges are ensuring redundant computation for error detection and guaranteeing diverse redundancy to detect errors even when they affect all replicas. Current solutions are limited and mostly focused on NVIDIA GPUs. This thesis presents a software-only solution for diverse redundancy on Intel GPUs, providing strong diversity guarantees for the first time. Built on OpenCL, a hardware-agnostic

Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as autonomous driving systems. However, the integration of complex, parallel, and computationally demanding software functions with different safety-criticality levels on GPU devices with shared hardware resources contributes to several safety certification challenges. This survey categorizes and provides an overview of research contributions that address GPU devices’ random hardware failures, systematic failures, and independence of execution., This work has been partially supported by the European Research Council with Horizon 2020 (grant agreements No. 772773 and 871465), the Spanish Ministry of Science and Innovation under grant PID2019-107255GB, the HiPEAC Network of Excellence and the Basque Government under grant KK-2019-00035. The Spanish Ministry of Economy and Competitiveness has also partially supported Leonidas Kosmidis with a Juan de la Cierva Incorporación postdoctoral fellowship (FJCI-2020- 045931-I)., Peer Reviewed, Postprint (author's final draft)

The need for increased application performance in high-integrity systems like those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products are multi-processors systems-on-chip (MPSoC) processors. MPSoCs include CPU multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (GPUs) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExt) in current COTS processors for high-integrity systems. We show that VExt prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExt require no runtime support, prevent by design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExt provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExt are the DPA approach with arguably the fastest path for adoption in high-integrity systems., This work has received funding from the the European Research Council (ERC) grant agreement No. 772773 (SuPerCom) and the Spanish Ministry of Science and Innovation (AEI/10.13039/501100011033) under grants PID2019-107255GB-C21 and IJC2020-045931-I., Peer Reviewed, Postprint (author's final draft)

There is an increasing trend in modern space systems to move processing that until now was transmitted to ground for processing, on board the satellite. Synthetic Aperture Radar (SAR) is an example of such processing. However, such a computationally intensive task requires high performance hardware. In this paper we present the CPU and GPU acceleration of an on-board SAR processing application, part of ESA's open source benchmarking suite OBPMark. We benchmark several embedded multicore and GPU platforms which are promising candidates for future on-board systems. Our results show that both embedded multicores and especially GPUs can provide significant speedups in this type of processing, and can achieve performance levels similar to the ones of high performance ground stations., This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) ESA-funded project. Moreover, it was supported by the European Union’s Horizon Europe programme under the METASAT project (grant agreement 101082622). It was also partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GBC21 and IJC-2020-045931-I ( Spanish State Research Agency / Agencia Espanola de Investigación (AEI) / http://dx.doi.org/10.13039/501100011033 ) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637)., Peer Reviewed, Postprint (author's final draft)

In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks will always take their Worst Case Execution Time (WCET), to make sure they meet their deadlines. For this reason, Worst Case Execution Times defines the maximum performance of processors in these systems. Since the performance requirements of modern Hard Real-time Systems are rapidly increasing, the use of newer and higher performance processors is needed. However, these processors have a much greater internal complexity compared to the ones previously used in these systems. This complexity can be detrimental given that Worst Case Execution Times, which are critical for these systems, are often estimated using traditional timing analysis methods like Static and Measurement-based deterministic techniques. The need for extremely detailed knowledge of the processor's internals, IP restrictions, and the impossibility of modeling certain features leads to extremely pessimistic assumptions and the disabling of features while using these techniques. On the other hand, Measurement-Based Probabilistic Timing Analysis (MBPTA) allows computing probabilistic WCET estimates easily on top of more complex hardware. This can only be performed when Time Randomisation is introduced in the microarchitectural design, e.g. namely through time-randomised cache designs. Despite their better WCET compared to conventional caches, time-randomised caches provide lower average performance. In this work, we perform the following contributions. First, we add MBPTA support in a commercial RISC-V processor for real-time systems. We show how branch prediction can become MBPTA-compliant, and in conjunction with a cache-locking mechanism can increase the front-end performance of an MBPTA compliant processor. Our evaluation demonstrates benefits both in terms of average case as well

In the domain of safety-critical systems there is an increasing need for more compute-capable and higher performance devices. This comes from the dramatic increase on the software complexity caused by the newest intelligent and autonomous systems. Graphics Processing Units (GPUs), as multi-processing accelerators, are an ideal choice in this aspect due to their ability to handle big amount of data and computations. In order to ease the challenging task of programming such devices, vendors are continuously adding features, such as Unified Memory (UM), which allow the programmers to reduce their developing time on GPU applications. However, the use of GPU poses several challenges on safety-critical systems due to its close source nature and proprietary implementation. Therefore, this paper shows a deeper insight on how this feature works and present a way of exploiting this knowledge to reduce the execution time of applications using NVIDIA's UM feature. We demonstrate that these optimizations can make the data migrations predictable and reduce the required time., This work was supported by the European Union’s Horizon Europe programme under the METASAT project (grant agreement 101082622). It was partially supported the Spanish Ministry of Economy and Competitiveness under grant IJC-2020-045931-I (Spanish State Research Agency / Agencia Espanola de Investigación (AEI) / http://dx.doi.org/10.13039/501100011033) and by the Basque Collaborative Research Grant Programme ELKARTEK under the AUTOTRUST project (KK-2023)., Peer Reviewed, Postprint (author's final draft)