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The binary-coded decimal (BCD) being the more accurate and human-readable representation with ease of conversion is prevailing in the computing and electronic communication. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity O(N(log2b)+(N-1)), where N = number of digits and b = number of bits in a digit. BCD adder is more effective with a lookup table (LUT)-based design, due to field programmable gate array (FPGA) technology’s enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. The proposed parallel BCD adder gains a radical achievement compared to the existing best known LUT-based BCD adders. The proposed BCD adder is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a -3 speed grade by using ISE 13.1. The proposed BCD adder provides prominent better performance with 20.0% reduction in area and 41.32% reduction in delay for the post-layout simulation. Since the proposed circuit is improved in both area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement. Moreover, the proposed design consumes 34.28% less power in comparison with existing best known approach at a clock frequency of 200 MHz and a reference voltage of 5 V. [ABSTRACT FROM AUTHOR]

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature. [ABSTRACT FROM PUBLISHER]

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition. [ABSTRACT FROM AUTHOR]

Traditional projection environments typically comprise projectors and custom-built projection screens in a static setting. However, with the availability of embedded and standalone pico-projectors, the representative use-case of such hand-held projectors is shifting from static to mobile. Users are increasingly using such devices to project content in random indoor environments that are cluttered and hence not completely suitable for projection. This paper proposes a robust binary-coded pattern that enables the reliable selection of a clutter-free sub-surface from within the projected area and thus allows the confinement of projection to the selected sub-region. Experiments confirm that the proposed pattern provides better resilience to the detection errors as compared to the state-of-the-art binary-coded patterns for the case of mobile-grade low-resolution pico-projectors. [ABSTRACT FROM AUTHOR]

We construct binary codes for fingerprinting digital documents. Our codes for n users that are -secure against c pirates have length O(c² log(n/ϵ)). This improves the codes proposed by Boneh and Shaw [1998] whose length is approximately the square of this length. The improvement carries over to works using the Boneh-Shaw code as a primitive, for example, to the dynamic traitor tracing scheme of Tassa [2005]. By proving matching lower bounds we establish that the length of our codes is best within a constant factor for reasonable error probabilities. This lower bound generalizes the bound found independently by Peikert et al. [2003] that applies to a limited class of codes. Our results also imply that randomized fingerprint codes over a binary alphabet are as powerful as over an arbitrary alphabet and the equal strength of two distinct models for fingerprinting. [ABSTRACT FROM AUTHOR]

We prove that arbitrary n-ary quasigroups of order 4 can be transformed into each other by successive switchings of {a, b}-components. We prove that perfect (closely packed) binary codes with distance 3 whose rank (dimension of the linear span) is greater by 1 or 2 than the rank of a linear perfect code can be taken to each other by successive switchings of i-components. [ABSTRACT FROM AUTHOR]

In this paper, we give three new constructions of binary sequences of period 4N with optimal autocorrelation value or optimal autocorrelation magnitude using N x 4 interleaved sequences. Yu and Gong recently found any binary sequence of period 4N with optimal autocorrelation value constructed from an almost difference set by Arasu et al. is an N x 4 interleaved sequence for which all four columns in its N x 4 array are shift equivalent up to the complement. We found that it is not necessary that four columns are shift equivalent. Instead, it could be a pair of related sequences together with their shifts as the column sequences. The first construction is to use a generalized GMW sequence of period N = 22k - 1 and its modified version, the second construction is to use a twin prime sequence of length N = p(p + 2) and its modified version, and the third construction, a pair of Legendre sequences of period N = p (p odd prime) with their respective first terms complementary (the 2-level autocorrelation property is not needed for the Legendre sequence). The comparison with the known constructions are given. For the new sequences with optimal autocorrelation value, their corresponding new almost difference sets are also derived. [ABSTRACT FROM AUTHOR]

We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding [ABSTRACT FROM AUTHOR]

Consider the case where consecutive blocks of N letters of a semi-infinite individual sequence X over a finite alphabet are being compressed into binary sequences by some one-to-one mapping. No a priori information about X is available at the encoder, which must therefore adopt a universal data-compression algorithm. It is known that there exist a number of asymptotically optimal universal data compression algorithms (e.g., the Lempel—Ziv (LZ) algorithm, Context tree algorithm and an adaptive Hufmann algorithm) such that when successively applied to N-blocks then, the best error-free compression for the particular individual sequence X is achieved as N tends to infinity. The best possible compression that may be achieved by any universal data compression algorithm for finite N-blocks is discussed. Essential optimality for the compression of finite-length sequences is defined. It is shown that the LZ77 universal compression of N-blocks is essentially optimal for finite N-blocks. Previously, it has been demonstrated that a universal context tree compression of N blocks is essentially optimal as well. [ABSTRACT FROM AUTHOR]

Abstract: Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well. [Copyright &y& Elsevier]

The performance of punctured low-definition parity-check (LDPC) codes under maximum-likelihood (ML) decoding is studied in this correspondence via deriving and analyzing their average weight distributions (AWDs) and the corresponding asymptotic growth rate of the AWDs. In particular, it is proved that capacity-achieving codes of any rate and for any memoryless binary-input output-symmetric (MBIOS) channel under ML decoding can be constructed by puncturing some original LDPC code with small enough rate. Moreover, it is shown that the gap to capacity of all the punctured codes can be the same as the original code with a small enough rate. Conditions under which puncturing results in no rate loss with asymptotically high probability are also given in the process. These results show high potential for puncturing to be used in designing capacity-achieving codes, and in rate-compatible coding under any MBIOS channel. [ABSTRACT FROM AUTHOR]

Abstract: Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272–282] recently proposed, in this journal, a reversible adder for binary-coded decimals. This paper corrects and optimizes their design. The optimized 1-decimal BCD full-adder, a 13×13 reversible logic circuit, is faster, and has lower circuit cost and less garbage bits. It can be used to build a fast reversible m-decimal BCD full-adder that has a delay of only m +17 low-power reversible CMOS gates. For a 32-decimal (128-bit) BCD addition, the circuit delay of 49 gates is significantly lower than is the number of bits used for the BCD representation. A complete set of reversible half- and full-adders for n-bit binary numbers and m-decimal BCD numbers is presented. The results show that special-purpose design pays off in reversible logic design by drastically reducing the number of garbage bits. Specialized designs benefit from support by reversible logic synthesis. All circuit components required for optimizing the original design could also be synthesized successfully by an implementation of an existing synthesis algorithm. [Copyright &y& Elsevier]

With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations. [ABSTRACT FROM AUTHOR]

B. E. Wampold, T. Minami, S. C. Tierney, T. W. Baskin, and K. S. Bhati (2005) re-analyzed trials included in our systematic review of randomized clinical trials that compared placebo with no treatment (A. Hróbjartsson & P. C. Gøtzsche, 2001). Based on 11 trials, B. E. Wampold et al. concluded that “ ... the placebo effect is robust” (p. 850). We (2001) concluded, based on 130 trials, that “we found little evidence in general that placebos have powerful clinical effects” (p. 1599). In this commentary, we examine the reasons for this discrepancy. For trials with continuous outcomes, our analyses (82 trials) and that of B. E. Wampold et al. (5 trials) resulted in pooled standardized mean differences that were small and essentially identical: -0.28 (95% confidence interval = -0.38 to -0.19) versus -0.29 (95% confidence interval = -0.52 to -0.06). There was considerable risk of bias (e.g., reporting bias, sample-size bias). Similarly, for trials with binary outcomes, our analysis (32 trials) and that of B. E. Wampold et al. (6 trials) found no statistically significant pooled effect of placebo interventions and were essentially identical: relative risk 0.95 (95% confidence interval = 0.88–1.02) versus odds ratio 0.99 (95% confidence interval = 0.81–1.23). Thus, B. E. Wampold et al.'s conclusion was not substantiated by their data, and is best characterized as powerful spin. © 2007 Wiley Periodicals, Inc. J Clin Psychol 63: 373–377, 2007. [ABSTRACT FROM AUTHOR]

In this paper, we show that a recently proposed algorithm for decoding cyclic codes may be applied efficiently to all binary cyclic codes with t ⩽ 2 and n < 63. This is accomplished by providing structure theorems for the codes in this range and classifying the relevant cases. [ABSTRACT FROM AUTHOR]

Some questions related to the computation of the capacity of codes that avoid forbidden difference patterns are analysed. The maximal number of n-bit sequences whose pairwise differences do not contain some given forbidden difference patterns is known to increase exponentially with n; the coefficient of the exponent is the capacity of the forbidden patterns. In this paper, new inequalities for the capacity are given that allow for the approximation of the capacity with arbitrary high accuracy. The computational cost of the algorithm derived from these inequalities is fixed once the desired accuracy is given. Subsequently, a polynomial time algorithm is given for determining if the capacity of a set is positive while the same problem is shown to be NP-hard when the sets of forbidden patterns are defined over an extended set of symbols. Finally, the existence of extremal norms is proved for any set of matrices arising in the capacity computation. Based on this result, a second capacity approximating algorithm is proposed. The usefulness of this algorithm is illustrated by computing exactly the capacity of particular codes that were only known approximately. [ABSTRACT FROM AUTHOR]

The nonlinear span of a sequence x is defined as the length of the shortest feedback shift register that generates x. In this correspondence, we solve the problem of designing periodic binary sequences with given linear complexity and maximal possible nonlinear span. We concentrate on the case of sequences with period N = 2n- 1 and we introduce two construction methods. [ABSTRACT FROM AUTHOR]

In this paper, we solve the classic problem of computing the average number of decomposed quadtree blocks (quadrants, nodes, or pieces) in quadtree decomposition for an arbitrary hyperrectangle aligned with the axes. We derive a closed-form formula for general cases. The previously known state-of-the-art solution provided a closed-form solution for special cases and utilized these formulas to derive linearly interpolated formulas for general cases individually. However, there is no exact and uniform closed-form formula that fits all cases. Contrary to the top-down counting approach used by most prior solutions, we employ a bottom-up enumeration approach to transform the problem into one that involves the Cartesian product of d multisets of successive 2's powers. Classic combinatorial enumeration techniques are applied to obtain an exact and uniform closed-form formula. The result is of theoretical interest since it is the first exact closed-form formula for arbitrary cases. Practically, it is nice to have a uniform formula for estimating the average number since a simple program can be conveniently constructed taking side lengths as inputs. [ABSTRACT FROM AUTHOR]

This correspondence revisits the idea of constructing a binary [m n, mk] code from an [n, k] code over F2m by concatenating the code with a suitable basis representation of F2m over F2. We construct two nonequivalent examples of doubly even self-dual binary codes of length 160 which turn out to be of minimum distance 24. This improves the lower bound for this class of codes, whereas the upper bound Is given by 28. The construction at hand seems to be of interest beyond this particular example. [ABSTRACT FROM AUTHOR]

The almost sure rate of convergence of linear stochastic approximation algorithms is analyzed in this correspondence. As the main result, it is demonstrated that their almost sure rate of convergence is equivalent to the almost sure rate of convergence of the averages of their input data sequences. As opposed to most of the existing results on the rate of convergence of stochastic approximation which cover only algorithms with the noise decomposable as the sum of a martingale difference, vanishing and telescoping sequence, the main results of this correspondence hold under assumptions not requiring the input data sequences to admit any particular decomposition. Although no decomposition of the input data sequences is required, the results on the almost sure rate of convergence of linear stochastic approximation algorithms obtained in this correspondence are as tight as the rate of convergence in the law of iterated logarithm. Moreover, the main result of this correspondence yields the law of iterated logarithm for linear stochastic approximation if the law of iterated logarithm holds for the input data sequences. The obtained general results are illustrated with two (nontrivial) examples where the input data sequences are strongly mixing strictly stationary random processes or functions of a uniformly ergodic Markov chain. These results are also applied to the analysis of least mean square (LMS) algorithms. [ABSTRACT FROM AUTHOR]

An efficient algorithm for calculating the ith bit error probability of a binary linear code over the binary symmetric channel (BSC) is presented. It is proved that the exact ith bit error probability of maximum-likelihood (ML) decoding, bounded distance decoding, and symbol-wise maximum a posteriori probability (MAP) decoding can be obtained with time complexity O(n2n-k), where n and k denote the length and the dimension of the target code. The proposed methods are applicable to any binary linear code with redundancy up to nearly 25-30 bits with a typical personal computer. [ABSTRACT FROM AUTHOR]

The success of genetic searches greatly depends on appropriate selections for many search parameters. This situation becomes more critical for optimization problems involving sharp constraint surfaces. When penalty function approaches are used to handle the constraints, the genetic algorithm conducts the search on a design space which has continually changing contours during the evolution. This often leads to incorrect gene extinctions at early stages of the search, and thus prevents the search from attaining the final global solution. This paper aims to devise a hybrid-coded crossover strategy for binary-coded genetic algorithms (BGA) which combines the major content of two-point crossover and the full domain representation characteristics embedded in many crossover schemes of real-coded genetic algorithms. It is found that the unique hybrid-coded crossover scheme can largely prevent the binary-coded genetic searches from falsely converging to sub-optimal solutions. Comparisons between BGA with the hybrid-coded crossover and the traditional two-point crossover are conducted in a number of illustrative problems with varied combinations of constraints. [ABSTRACT FROM AUTHOR]

We show that the dual code of the binary cyclic code of length 2m−1 with two zeros α,αd cannot have three weights in the case that m is even and d≡0 (mod 3). The proof involves the partial calculation of a coset weight distribution. [Copyright &y& Elsevier]

We consider the search problem in which one finds a binary word among m words chosen randomly from the set of all words of fixed length n. It is well known that the optimal search is equivalent to the Huffman coding that requires on average log[sub 2] m bits to be checked plus a small additional cost called the average redundancy, The latter is an oscillating function of m and is bounded between zero and 1 - (1 + ln ln 2)/ln 2 ≈ 0.0860713320. As a matter of fact, it is known that finding the optimal strategy for this problem is NP-hard. We propose here several simply randomized search strategies leading, respectively, to the following average redundances: 1.332746177, 0.6113986565, 0.4310617764, and 0.332746177, plus some small oscillations that we precisely characterize. These results should be compared to the optimal, but NP-hard, search algorithm. Our findings extend and make more precise recent results of Fedotov and Ryabko. [ABSTRACT FROM AUTHOR]

Presents a recursive method for the construction of optimal one-ended binary codes. Definition of one-ended codes; Operations for improving length vectors; Facts on the restriction of the set of optimal multiplicity vectors.

Presents a study on self-orthogonal binary codes supporting designs. Description of invariant linear forms and designs; Discussion on five-designs.

Frameproof codes (FPCs) are widely studied as they are classic fingerprinting codes that can protect copyrighted materials. The main interests are construction methods and bounds of the number of codewords of FPCs for a fixed length when the alphabet size approaches infinity. In this paper, we focus on the upper bound of the size of FPCs when the fixed length is 4 and the strength is 2. We obtain an upper bound 2q2-2q+7 on the size of a q-ary 2-FPC of length 4 for any positive integer q>48. The best previously well known bound of this type of FPCs is 2q2-2, which is due to Blackburn (SIAM J Discret Math 16:499-510, 2003). Our new upper bound improves the previous upper bound and it is not very far from the current best lower bound 2q2-4q+3 obtained from the explicit construction due to Chee and Zhang (IEEE Trans Inf Theory 58:5449-5453, 2012). [ABSTRACT FROM AUTHOR]

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a technique for the conversion of the residue number of the equivalent binary coded decimal number using counter circuitry. The conversion process is not limited by the residue number-system moduli. The test circuit was operated with a 1 MHz clock pulse. [ABSTRACT FROM AUTHOR]

This paper presents a logic design for a new decimal-digit parallel adder. The output decimal carry delay time is reduced and the addition speed of two BCD numbers is improved. The inter-stage output carries of a binary adder are essentially eliminated. Also the hardware is economized. The corrected decimal sums and output carry are produced simultaneously, in contrast with the conventional method, whose decimal sums are delayed after the output carry. [ABSTRACT FROM AUTHOR]

This paper presents a new method for converting binary-to-BCD and BCD-to-binary using up/down counters. This method is compared with Couleur's two-step process and also with Rhyne's one-step process. If the slow speed operation is not critical, the implementation of the proposed converter is very easy. The circuit is also quite flexible. A synchronous four-bit up/down counter (binary as well as decade) is available from the shelf in one package. These counters can be cascaded without need for external circuitry. This conversion is reversible without changing the circuitry or circuit element, simply by changing the mode control equal to law or high level. The conversion can be performed from one code number to any other code number system, even two or three different code systems, i.e. multi-channel conversion is possible. [ABSTRACT FROM AUTHOR]

Presents information on a study which focused on a construction of decodable codes for the two-user binary adder channel. Code construction; Properties of codes constructed by (u)-(v); Decoding algorithm; Enumerative coding.

Presents information on a study which focused on the aperiodic crosscorrelation of binary codes. Weighted cyclic shifts; Reduction to quadratic form and optimization.

Presents information on a study which determined the weight hierarchies of linear binary codes of dimension four. Notations and problem formulation; Proof of the bounds.

Presents information on a study which evaluated the alphabet F... + uF... binary code as a quotient of the Gaussian integers. Notations and definitions; Properties of Type II binary codes; Structure of the Type II codes; Classification.

Presents a study which derived several lower bounds on the size of binary codes with covering radius one. Proof of the theorems.

Presents a study which evaluated an adaptive sequential prediction of arbitrary binary sequences using general loss function. Performance of on-line learning; Details on the algorithm and the upper bounds; Results.

Considers some binary linear codes of length using the adjacency matrices of the Hoffman-Singleton graph and the Higman-Sims graph. How binary linear codes with parameters are constructed; Conclusions.

Explores the incompatibilities of the hardware- and software-optimized binary arithmetic coding conventions, the Q-coder and the QM-coder. Solution that allowed a merged Qx-coder in hardware; Hardware for the termination of the Joint Bi-level Image Experts Group (JBIG) data stream (CLEARBITS); Common format for probability estimation.

In the conventional coding of the facsimile signal, codes such as modified Huffman (MH) and modified Reed (MMR) codes have been used, where the statistical properties of the image are assumed as known and the image is assumed as stationary. In practice, however, it is not always adequate to represent the probabilistic structure of the image data by a single model. It is desirable to employ a code whose coding parameters can be adjusted according to the variation of the statistical properties. The arithmetic code can realize independently the symbol coding and the probability estimation, and the dynamic, modification of the coding parameters is easy. From such a viewpoint, this paper proposes a new dynamic adaptive coding based on the arithmetic code. In the proposed method, the effective probability of the less probable symbol, which is the coding parameter of the arithmetic symbol, is selected from the values obtained by the approximation using a polynomial sum of the powers of 2. The algorithm of transition in each coding parameter is determined by considering both the static and the dynamic coding characteristics. In addition, a method is presented in which the decision about the stationarity is included, and the convergence from the initial value is improved by controlling the number of transition steps. As a result of simulation, it is seen that the proposed method can reduce the number of bits of the coded output by 27.2 percent on the average, compared to MMR coding. [ABSTRACT FROM AUTHOR]

The article provides information on an activity on the converting Binary-Coded Decimal (BCD) to Seven-Segment Decoder by counting coins. The activity requires seven coins labeled with numbers, a placemat, and a pen or marker. An illustration is offered to help students understand how to convert between decimal and binary numbers. Test questions for students before and after the activity are presented.

Decimal X\times Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix- 10~X multiples. Some works require only [ 0, 5 ]\times X via recoding digits of Y to one-hot representation of signed digits in $ [-5, 5]$ . This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one xor per bit of $X$ multiples) is required for the recoded digits of $Y$ in $[-5, -1]$ . In this paper, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save 75% of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:1 reduction leads to two TCSD accumulated partial products, which collectively undergo a special early initiated conversion scheme to get at the final binary-coded decimal product. As such, a VLSI implementation of $16\times 16$ -digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs. [ABSTRACT FROM AUTHOR]