Using a micro-core architecture in a modem scalar processor

A computer modem consists of many processors and memories, specialized for digital signal processing. One of the components, the main scalar processor, may also consist of multiple processor cores. This thesis investigates the approach of specializing these further, cutting features such as supported instructions or pipeline stages where possible, in order to save area and improve performance. These specialized processor cores, in this thesis called micro-cores, would then be combined in a heterogeneous chip, which together supports the entire instructionset. The investigation found that micro-cores can save significant area, and even improve general-purpose performance; however, a large investigation with more complex cores and a final integration, would be required to completely evaluate the design approach. Still, this investigation provides valuable insight into processor design; such as what contributes to chip area and how new components or more pipelining affects processor speed and program performance.