Stacked Complementary Field-Effect Transistors: Promises and Challenges

This paper presents a thorough review of the evolution of Stacked Complementary Field-Effect transistors (CFET), including earlier work and recent demonstrations. The study outlines the challenges encountered during the fabrication process, such as insulator formation between active layers, deep ion implantation for bottom devices, selective contact between top and bottom transistors, and the layout of stacked transistors. Additionally, this paper explores the potential extension of the CFET technology and its integration with emerging device structures and advanced materials, such as 2D transistors. By analyzing these possibilities, this study sheds light on the potential for further advancements and applications of the CFET technology. © 2024 IEEE.