Hardware-software co-design of an iris recognition algorithm

This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40MHz, an IrisCode is obtained in <523ms from an image of 640×480 pixels, which is just 20 of the total time needed by a software solution running on the same microprocessor embedded in the architecture. © 2011 The Institution of Engineering and Technology.