A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration

Power-efficient ADCs are widely in demand in multi-channel high-resolution analog frontends (e.g., medical imaging), where the SAR architecture is highly favored due to its Nyquist-rate nature, excellent power efficiency, and compatibility with process scaling [1]-[5]. However, the kT/C noise becomes a key bottleneck in high-resolution SAR ADCs (>q 16b). To achieve lower kT/C noise, [2]-[5] increase the total capacitance (e.g., > 10pF for a 16b noise level with a 6.6Vpp swing) of the CDAC at the price of increased area and higher power. A kT/C noise cancelation technique is presented in [6] to reduce the kT/C noise with a small DAC. As shown in Fig. 1 (top-left), In this scheme, the input is connected to the DAC during autozeroing (AZ), requiring a short Taz to prevent the changing input from saturating the amplifier. A short Taz requires a high AZ bandwidth for proper settling, which inevitably aliases the amplifier's wideband noise, requiring a power-hungry low-noise pre-amplifier for high-resolution ADCs. This paper proposes a 16b SAR ADC with the split sampling (SS) that decouples the sampling and conversion operations to effectively address the above tradeoff, enabling a low AZ bandwidth and achieving low noise and low power. © 2024 IEEE.