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CMOS-compatible Manufacturing of Room-Temperature Single Electron Transistors
- Source :
- EMRS 2022 Fall Meeting, 19.-22.09.2022, Warsaw, Poland
- Publication Year :
- 2022
-
Abstract
- Low-power logic and memory circuits remain a main task for the next generations of energy-efficient electronic devices. Single Electron Transistors (SETs) are extremely low energy dissipation devices. However, SETs operate usually at cryogenic temperatures and have some serious drawbacks. Fortunately, Field Effect Transistors (FETs) and SETs are complementary: The SET is the champion of low-power consumption while FETs advantages, like high-speed, driving, voltage gain and input impedance can compensate exactly for SET's intrinsic drawbacks. To overcome the drawback of cryogenic temperature operation, each SET has to be manufactured with a quantum dot of a size of just a few nanometers, and this dot has to be located not more than about one nanometer apart from the electrodes. The large-scale implementation of SETs in room-temperature electronics is hampered by its unresolved manufacturability because such requirements are beyond the limits of present lithography. We employed self-organization to overcome the present-day limits of lithography. On 5…8nm thick SiO2 layers of (001)Si wafers about 30nm thick a-Si layers have been deposited and subsequently irradiated with 50 keV Si+ ions. The irradiation leads to ion beam mixing at the upper and lower Si/SiO2 interfaces and transforms the buried SiO2 layer to SiOx with x~1. Then, pillar arrays have been fabricated from such layer stacks using electron beam lithography and plasma etching. Arrays of pillars with different diameters from 100nm down to less than 20nm have been produced, where the smallest pillar diameters have been further reduced to ~10nm by plasma oxidation and selective oxide etching (sacrificial oxidation). In this manner we manufactured SiOx disks of ~10nm diameter and 5nm thickness sandwiched between the Si of the pillars. During Rapid Thermal Processing (RTP) of such pillars at 1050°C for 60s, phase separation SiOx (1-x/2)Si + x/2SiO2 occurs via formation of Si nuclei and Ostwald ripening. Close to
Details
- Database :
- OAIster
- Journal :
- EMRS 2022 Fall Meeting, 19.-22.09.2022, Warsaw, Poland
- Notes :
- English
- Publication Type :
- Electronic Resource
- Accession number :
- edsoai.on1415609427
- Document Type :
- Electronic Resource