Simulating spin systems on IANUS, an FPGA-based computer

© 2007 Elsevier B.V. Artículo firmado por 18 autores. The help of G. Poli in the development of the IANUS Ethernet interface is warmly acknowledged.
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
Depto. de Física Teórica
Fac. de Ciencias Físicas
TRUE
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