Streamlined NTRU Prime on FPGA

MLA

Peng, Bo-Yuan, et al. Streamlined NTRU Prime on FPGA. 2022. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsoai&AN=edsoai.on1390834771&authtype=sso&custid=ns315887.

APA

Peng, B.-Y., Marotzke, A., Tsai, M.-H., Yang, B.-Y., & Chen, H.-L. (2022). Streamlined NTRU Prime on FPGA.

Chicago

Peng, Bo-Yuan, Adrian Marotzke, Ming-Han Tsai, Bo-Yin Yang, and Ho-Lin Chen. 2022. “Streamlined NTRU Prime on FPGA.” http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsoai&AN=edsoai.on1390834771&authtype=sso&custid=ns315887.