Statistical analyses of intrinsic noise and variability effects in CMOS digital latches

The MOS transistors of minimal gate length, universally favoured for the design of digital integrated circuits, are very sensitive to process variability and intrinsic noise. Time-domain characterization of the noise in individual tran- sistors is the starting point of this thesis. In 28 nm FD-SOI, we have observed random telegraph noise (RTN) whose relative current variation can reach 30% in weak inversion. Accurate characterization and compact modelling of such noise, as well as efficient and insightful simulation methodology that would rely on a rigorous and solid mathematical foundation, are therefore required toward assessment and prediction of circuit reliability. We have extensively studied the impact of the process variability and the intrinsic noise on the functionality of ultra-low power (ULP) SRAM bitcells in retention mode. We propose a non- Monte-Carlo methodology for fast and accurate calculation of the subthreshold SRAM hold static stability failure rate with a closed-form formula, which we illustrate on a 28 nm FD-SOI 6T SRAM design operating at ultra-low sup- ply voltage. We combine computationally intensive transient noise simulations and mathematical analyses to observe and predict transient bit flips due to the combined effects of the RTN and of the flicker noise and thermal noise sources. We conclude that, while process variability remains the major concern in 28 nm technology and beyond, experimentally measured RTN significantly reduce the noise margins and can severely endanger the dynamic stability of the latch.
(FSA - Sciences de l'ingénieur) -- UCL, 2022