Variability-aware parametric yield estimation for analog/mixed-signal circuits: Concepts, algorithms, and challenges

The undesired uncertainties in circuit performance can lead to analog/mixed-signal circuit failures and yield loss at nanoscale. As such, it has become extremely critical for high precision analog/RF circuits such as phase-locked loop (PLL) and custom/mixed-signal circuits such as SRAM arrays, which both have tight operating margin due to lower power supply and higher operating frequency. Many performance-domain techniques have become available in past few decades: the Monte Carlo (MC) method repeatedly draws samples, runs simulations, and evaluates the yield rate, which can be easily applied to high-dimensional problems. However, it is extremely time consuming. IS can reduce the number of samples required to achieve a desired accuracy, especially in the case where the failure region is small for rare failure events. However, it is always challenging to obtain an optimal sampling distribution or shift vector efficiently.