Short Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison with SiC MOSFETs

Although the GaN-HEMT/SiC-JFET cascode device exhibits certain performance advantages over the SiC MOSFET, its robustness in harsh operating conditions is unknown. In this work, the short circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots and thermal simulation results, thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad.