Izhikevich neural model and STDP learning algorithm mapping on spiking neural network hardware emulator

From the 20th century, biological mechanisms of the brain behaviour have become more and more interesting for the research communities in information fields due to the computational power of the systems they inspire. In fact, despite the lack of consensus about the information processing actually involved in brain, biological processes have served as reference for recent computational models. The first Artificial Neural Networks (ANNs) were developed as simplified versions of biological neural net- works in terms of structure and function. Today, the third generation of artificial network is that of the Spiking Neural Networks (SNNs), which reach a more realistic modelling by utilizing true biological features, like spikes, to transmit information between neurons. The proposal of this thesis is to embed the Izhikevich neuron model and a full custom "Spike timing dependent plasticity" (STDP) learning algorithm in an architecture called HEENS (Hardware Emulator of Evolved Neural System). HEENS is a multi-chip structure developed at the "Universitat Politecnica de Catalunya" (UPC) based on a ring link topology connecting several SIMD processors reproducing each one a group of neuron of a Spiking neural network. The Izhikevich neuron model is a worldwide adopted mathematical model for reproducing the neural membrane potential evolution, observed in some mammalian cortex, a long time and according to external stimuli. STDP is a biological learning algorithm which shapes the strength of a synaptic connection according to the timing with which that connection takes part to the overall spiking activity of the post or pre-synaptic neurons. This master thesis project, in particular, acts at algorithm level and at instruction level as well at architectural level. It takes place analysing the mathematical models for the right data parallelism, writing the assembly program describing the routine common to all the neurons of the implemented SNN, modifying the instruction set and