Real-time implementation with FPGA-based DAQ system of a probabilistic disruption predictor from scratch

Real-time (RT) disruption prediction (DP) is essential to trigger mitigation actions that avoid irreversible damage to the devices. This paper deals with disruption mitigation alarms and performs the RT implementation of a probabilistic predictor. The RT implementation has been carried out with a fast controller with DAQ FPGA-based data acquisition devices corresponding to ITER catalogue (in particular, a reconfigurable Input/Output platform has been used). Up to three input signals have been used and relevant information for the prediction is extracted from the temporal and the frequency domains. The signals are read from the JET database. Then D/A conversions are carried out and used as inputs to the real time system. In this way, the whole process of digitization, data analysis and prediction is performed. The computation time for each prediction takes less than 200 mu s.
For complete list of authors see http://dx.doi.org/10.1016/j.fusengdes.2018.02.071